xref: /kernel/linux/linux-5.10/arch/m68k/q40/config.c (revision 8c2ecf20) 
1/*
2 *  arch/m68k/q40/config.c
3 *
4 *  Copyright (C) 1999 Richard Zidlicky
5 *
6 * originally based on:
7 *
8 *  linux/bvme/config.c
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License.  See the file README.legal in the main directory of this archive
12 * for more details.
13 */
14
15#include <linux/errno.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/mm.h>
19#include <linux/tty.h>
20#include <linux/console.h>
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <linux/major.h>
24#include <linux/serial_reg.h>
25#include <linux/rtc.h>
26#include <linux/vt_kern.h>
27#include <linux/bcd.h>
28#include <linux/platform_device.h>
29
30#include <asm/io.h>
31#include <asm/bootinfo.h>
32#include <asm/setup.h>
33#include <asm/irq.h>
34#include <asm/traps.h>
35#include <asm/machdep.h>
36#include <asm/q40_master.h>
37
38extern void q40_init_IRQ(void);
39static void q40_get_model(char *model);
40extern void q40_sched_init(irq_handler_t handler);
41
42static int q40_hwclk(int, struct rtc_time *);
43static unsigned int q40_get_ss(void);
44static int q40_get_rtc_pll(struct rtc_pll_info *pll);
45static int q40_set_rtc_pll(struct rtc_pll_info *pll);
46
47extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
48
49static void q40_mem_console_write(struct console *co, const char *b,
50				  unsigned int count);
51
52extern int ql_ticks;
53
54static struct console q40_console_driver = {
55	.name	= "debug",
56	.write	= q40_mem_console_write,
57	.flags	= CON_PRINTBUFFER,
58	.index	= -1,
59};
60
61
62/* early debugging function:*/
63extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
64static int _cpleft;
65
66static void q40_mem_console_write(struct console *co, const char *s,
67				  unsigned int count)
68{
69	const char *p = s;
70
71	if (count < _cpleft) {
72		while (count-- > 0) {
73			*q40_mem_cptr = *p++;
74			q40_mem_cptr += 4;
75			_cpleft--;
76		}
77	}
78}
79
80static int __init q40_debug_setup(char *arg)
81{
82	/* useful for early debugging stages - writes kernel messages into SRAM */
83	if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
84		/*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
85		_cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
86		register_console(&q40_console_driver);
87	}
88	return 0;
89}
90
91early_param("debug", q40_debug_setup);
92
93#if 0
94void printq40(char *str)
95{
96	int l = strlen(str);
97	char *p = q40_mem_cptr;
98
99	while (l-- > 0 && _cpleft-- > 0) {
100		*p = *str++;
101		p += 4;
102	}
103	q40_mem_cptr = p;
104}
105#endif
106
107static int halted;
108
109#ifdef CONFIG_HEARTBEAT
110static void q40_heartbeat(int on)
111{
112	if (halted)
113		return;
114
115	if (on)
116		Q40_LED_ON();
117	else
118		Q40_LED_OFF();
119}
120#endif
121
122static void q40_reset(void)
123{
124	halted = 1;
125	pr_info("*******************************************\n"
126		"Called q40_reset : press the RESET button!!\n"
127		"*******************************************\n");
128	Q40_LED_ON();
129	while (1)
130		;
131}
132
133static void q40_halt(void)
134{
135	halted = 1;
136	pr_info("*******************\n"
137		"  Called q40_halt\n"
138		"*******************\n");
139	Q40_LED_ON();
140	while (1)
141		;
142}
143
144static void q40_get_model(char *model)
145{
146	sprintf(model, "Q40");
147}
148
149static unsigned int serports[] =
150{
151	0x3f8,0x2f8,0x3e8,0x2e8,0
152};
153
154static void __init q40_disable_irqs(void)
155{
156	unsigned i, j;
157
158	j = 0;
159	while ((i = serports[j++]))
160		outb(0, i + UART_IER);
161	master_outb(0, EXT_ENABLE_REG);
162	master_outb(0, KEY_IRQ_ENABLE_REG);
163}
164
165void __init config_q40(void)
166{
167	mach_sched_init = q40_sched_init;
168
169	mach_init_IRQ = q40_init_IRQ;
170	mach_hwclk = q40_hwclk;
171	mach_get_ss = q40_get_ss;
172	mach_get_rtc_pll = q40_get_rtc_pll;
173	mach_set_rtc_pll = q40_set_rtc_pll;
174
175	mach_reset = q40_reset;
176	mach_get_model = q40_get_model;
177
178#if IS_ENABLED(CONFIG_INPUT_M68K_BEEP)
179	mach_beep = q40_mksound;
180#endif
181#ifdef CONFIG_HEARTBEAT
182	mach_heartbeat = q40_heartbeat;
183#endif
184	mach_halt = q40_halt;
185
186	/* disable a few things that SMSQ might have left enabled */
187	q40_disable_irqs();
188
189	/* no DMA at all, but ide-scsi requires it.. make sure
190	 * all physical RAM fits into the boundary - otherwise
191	 * allocator may play costly and useless tricks */
192	mach_max_dma_address = 1024*1024*1024;
193}
194
195
196int __init q40_parse_bootinfo(const struct bi_record *rec)
197{
198	return 1;
199}
200
201/*
202 * Looks like op is non-zero for setting the clock, and zero for
203 * reading the clock.
204 *
205 *  struct hwclk_time {
206 *         unsigned        sec;       0..59
207 *         unsigned        min;       0..59
208 *         unsigned        hour;      0..23
209 *         unsigned        day;       1..31
210 *         unsigned        mon;       0..11
211 *         unsigned        year;      00...
212 *         int             wday;      0..6, 0 is Sunday, -1 means unknown/don't set
213 * };
214 */
215
216static int q40_hwclk(int op, struct rtc_time *t)
217{
218	if (op) {
219		/* Write.... */
220		Q40_RTC_CTRL |= Q40_RTC_WRITE;
221
222		Q40_RTC_SECS = bin2bcd(t->tm_sec);
223		Q40_RTC_MINS = bin2bcd(t->tm_min);
224		Q40_RTC_HOUR = bin2bcd(t->tm_hour);
225		Q40_RTC_DATE = bin2bcd(t->tm_mday);
226		Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
227		Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
228		if (t->tm_wday >= 0)
229			Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
230
231		Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
232	} else {
233		/* Read....  */
234		Q40_RTC_CTRL |= Q40_RTC_READ;
235
236		t->tm_year = bcd2bin (Q40_RTC_YEAR);
237		t->tm_mon  = bcd2bin (Q40_RTC_MNTH)-1;
238		t->tm_mday = bcd2bin (Q40_RTC_DATE);
239		t->tm_hour = bcd2bin (Q40_RTC_HOUR);
240		t->tm_min  = bcd2bin (Q40_RTC_MINS);
241		t->tm_sec  = bcd2bin (Q40_RTC_SECS);
242
243		Q40_RTC_CTRL &= ~(Q40_RTC_READ);
244
245		if (t->tm_year < 70)
246			t->tm_year += 100;
247		t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
248	}
249
250	return 0;
251}
252
253static unsigned int q40_get_ss(void)
254{
255	return bcd2bin(Q40_RTC_SECS);
256}
257
258/* get and set PLL calibration of RTC clock */
259#define Q40_RTC_PLL_MASK ((1<<5)-1)
260#define Q40_RTC_PLL_SIGN (1<<5)
261
262static int q40_get_rtc_pll(struct rtc_pll_info *pll)
263{
264	int tmp = Q40_RTC_CTRL;
265
266	pll->pll_ctrl = 0;
267	pll->pll_value = tmp & Q40_RTC_PLL_MASK;
268	if (tmp & Q40_RTC_PLL_SIGN)
269		pll->pll_value = -pll->pll_value;
270	pll->pll_max = 31;
271	pll->pll_min = -31;
272	pll->pll_posmult = 512;
273	pll->pll_negmult = 256;
274	pll->pll_clock = 125829120;
275
276	return 0;
277}
278
279static int q40_set_rtc_pll(struct rtc_pll_info *pll)
280{
281	if (!pll->pll_ctrl) {
282		/* the docs are a bit unclear so I am doublesetting */
283		/* RTC_WRITE here ... */
284		int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
285			  Q40_RTC_WRITE;
286		Q40_RTC_CTRL |= Q40_RTC_WRITE;
287		Q40_RTC_CTRL = tmp;
288		Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
289		return 0;
290	} else
291		return -EINVAL;
292}
293
294static __init int q40_add_kbd_device(void)
295{
296	struct platform_device *pdev;
297
298	if (!MACH_IS_Q40)
299		return -ENODEV;
300
301	pdev = platform_device_register_simple("q40kbd", -1, NULL, 0);
302	return PTR_ERR_OR_ZERO(pdev);
303}
304arch_initcall(q40_add_kbd_device);
305