18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/****************************************************************************/ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci/* 58c2ecf20Sopenharmony_ci * mcftimer.h -- ColdFire internal TIMER support defines. 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com> 88c2ecf20Sopenharmony_ci * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/****************************************************************************/ 128c2ecf20Sopenharmony_ci#ifndef mcftimer_h 138c2ecf20Sopenharmony_ci#define mcftimer_h 148c2ecf20Sopenharmony_ci/****************************************************************************/ 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci/* 178c2ecf20Sopenharmony_ci * Define the TIMER register set addresses. 188c2ecf20Sopenharmony_ci */ 198c2ecf20Sopenharmony_ci#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ 208c2ecf20Sopenharmony_ci#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 218c2ecf20Sopenharmony_ci#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 228c2ecf20Sopenharmony_ci#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 238c2ecf20Sopenharmony_ci#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 248c2ecf20Sopenharmony_ci#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 258c2ecf20Sopenharmony_ci#else 268c2ecf20Sopenharmony_ci#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ 278c2ecf20Sopenharmony_ci#endif 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci/* 308c2ecf20Sopenharmony_ci * Bit definitions for the Timer Mode Register (TMR). 318c2ecf20Sopenharmony_ci * Register bit flags are common across ColdFires. 328c2ecf20Sopenharmony_ci */ 338c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ 348c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ 358c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ 368c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ 378c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ 388c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ 398c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ 408c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ 418c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ 428c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ 438c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ 448c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ 458c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ 468c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ 478c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ 488c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ 498c2ecf20Sopenharmony_ci#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci/* 528c2ecf20Sopenharmony_ci * Bit definitions for the Timer Event Registers (TER). 538c2ecf20Sopenharmony_ci */ 548c2ecf20Sopenharmony_ci#define MCFTIMER_TER_CAP 0x01 /* Capture event */ 558c2ecf20Sopenharmony_ci#define MCFTIMER_TER_REF 0x02 /* Reference event */ 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci/****************************************************************************/ 588c2ecf20Sopenharmony_ci#endif /* mcftimer_h */ 59