18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/****************************************************************************/ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci/* 58c2ecf20Sopenharmony_ci * mcfpit.h -- ColdFire internal PIT timer support defines. 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci/****************************************************************************/ 118c2ecf20Sopenharmony_ci#ifndef mcfpit_h 128c2ecf20Sopenharmony_ci#define mcfpit_h 138c2ecf20Sopenharmony_ci/****************************************************************************/ 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci/* 168c2ecf20Sopenharmony_ci * Define the PIT timer register address offsets. 178c2ecf20Sopenharmony_ci */ 188c2ecf20Sopenharmony_ci#define MCFPIT_PCSR 0x0 /* PIT control register */ 198c2ecf20Sopenharmony_ci#define MCFPIT_PMR 0x2 /* PIT modulus register */ 208c2ecf20Sopenharmony_ci#define MCFPIT_PCNTR 0x4 /* PIT count register */ 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci/* 238c2ecf20Sopenharmony_ci * Bit definitions for the PIT Control and Status register. 248c2ecf20Sopenharmony_ci */ 258c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */ 268c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */ 278c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */ 288c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */ 298c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */ 308c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */ 318c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */ 328c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */ 338c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */ 348c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */ 358c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */ 368c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */ 378c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */ 388c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */ 398c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */ 408c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */ 418c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */ 428c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */ 438c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */ 448c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */ 458c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */ 468c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */ 478c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */ 488c2ecf20Sopenharmony_ci#define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */ 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci/****************************************************************************/ 518c2ecf20Sopenharmony_ci#endif /* mcfpit_h */ 52