1/* SPDX-License-Identifier: GPL-2.0 */ 2/****************************************************************************/ 3 4/* 5 * m525xsim.h -- ColdFire 525x System Integration Module support. 6 * 7 * (C) Copyright 2012, Steven king <sfking@fdwdc.com> 8 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) 9 */ 10 11/****************************************************************************/ 12#ifndef m525xsim_h 13#define m525xsim_h 14/****************************************************************************/ 15 16/* 17 * This header supports ColdFire 5249, 5251 and 5253. There are a few 18 * little differences between them, but most of the peripheral support 19 * can be used by all of them. 20 */ 21#define CPU_NAME "COLDFIRE(m525x)" 22#define CPU_INSTR_PER_JIFFY 3 23#define MCF_BUSCLK (MCF_CLK / 2) 24 25#include <asm/m52xxacr.h> 26 27/* 28 * The 525x has a second MBAR region, define its address. 29 */ 30#define MCF_MBAR2 0x80000000 31 32/* 33 * Define the 525x SIM register set addresses. 34 */ 35#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ 36#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 37#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ 38#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ 39#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ 40#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ 41#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 42#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ 43#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ 44#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ 45#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ 46#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ 47#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ 48#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ 49#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ 50#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ 51#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ 52#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ 53#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ 54 55#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ 56#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ 57#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ 58#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ 59#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ 60#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ 61#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ 62#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ 63#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 64#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ 65#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ 66#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 67#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ 68#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ 69#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 70 71#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 72#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 73#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ 74#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ 75#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ 76 77/* 78 * Secondary Interrupt Controller (in MBAR2) 79*/ 80#define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */ 81#define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */ 82#define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */ 83#define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */ 84#define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */ 85#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */ 86#define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */ 87#define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */ 88#define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */ 89 90#define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \ 91 ((((i) - MCFINTC2_VECBASE) / 8) * 4)) 92#define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4)) 93 94/* 95 * Timer module. 96 */ 97#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 98#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 99 100/* 101 * UART module. 102 */ 103#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ 104#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ 105 106/* 107 * QSPI module. 108 */ 109#define MCFQSPI_BASE (MCF_MBAR + 0x400) /* Base address QSPI */ 110#define MCFQSPI_SIZE 0x40 /* Register set size */ 111 112#ifdef CONFIG_M5249 113#define MCFQSPI_CS0 29 114#define MCFQSPI_CS1 24 115#define MCFQSPI_CS2 21 116#define MCFQSPI_CS3 22 117#else 118#define MCFQSPI_CS0 15 119#define MCFQSPI_CS1 16 120#define MCFQSPI_CS2 24 121#define MCFQSPI_CS3 28 122#endif 123 124/* 125 * I2C module. 126 */ 127#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base address I2C0 */ 128#define MCFI2C_SIZE0 0x20 /* Register set size */ 129 130#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base address I2C1 */ 131#define MCFI2C_SIZE1 0x20 /* Register set size */ 132 133/* 134 * DMA unit base addresses. 135 */ 136#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ 137#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ 138#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ 139#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ 140 141/* 142 * Some symbol defines for the above... 143 */ 144#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 145#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 146#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 147#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ 148#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 149#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 150#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 151#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 152#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 153#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 154#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ 155 156/* 157 * Define system peripheral IRQ usage. 158 */ 159#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */ 160#define MCF_IRQ_I2C0 29 161#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 162#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 163 164#define MCF_IRQ_UART0 73 /* UART0 */ 165#define MCF_IRQ_UART1 74 /* UART1 */ 166 167/* 168 * Define the base interrupt for the second interrupt controller. 169 * We set it to 128, out of the way of the base interrupts, and plenty 170 * of room for its 64 interrupts. 171 */ 172#define MCFINTC2_VECBASE 128 173 174#define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32) 175#define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33) 176#define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34) 177#define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35) 178#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36) 179#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37) 180#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38) 181#define MCF_IRQ_GPIO7 (MCFINTC2_VECBASE + 39) 182 183#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40) 184#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62) 185 186/* 187 * General purpose IO registers (in MBAR2). 188 */ 189#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ 190#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */ 191#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */ 192#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */ 193#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */ 194#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */ 195#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ 196#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ 197 198#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */ 199#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */ 200#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */ 201 202#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */ 203#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */ 204#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */ 205 206/* 207 * Generic GPIO support 208 */ 209#define MCFGPIO_PIN_MAX 64 210#ifdef CONFIG_M5249 211#define MCFGPIO_IRQ_MAX -1 212#define MCFGPIO_IRQ_VECBASE -1 213#else 214#define MCFGPIO_IRQ_MAX 7 215#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0 216#endif 217 218/****************************************************************************/ 219 220#ifdef __ASSEMBLER__ 221#ifdef CONFIG_M5249C3 222/* 223 * The M5249C3 board needs a little help getting all its SIM devices 224 * initialized at kernel start time. dBUG doesn't set much up, so 225 * we need to do it manually. 226 */ 227.macro m5249c3_setup 228 /* 229 * Set MBAR1 and MBAR2, just incase they are not set. 230 */ 231 movel #0x10000001,%a0 232 movec %a0,%MBAR /* map MBAR region */ 233 subql #1,%a0 /* get MBAR address in a0 */ 234 235 movel #0x80000001,%a1 236 movec %a1,#3086 /* map MBAR2 region */ 237 subql #1,%a1 /* get MBAR2 address in a1 */ 238 239 /* 240 * Move secondary interrupts to their base (128). 241 */ 242 moveb #MCFINTC2_VECBASE,%d0 243 moveb %d0,0x16b(%a1) /* interrupt base register */ 244 245 /* 246 * Work around broken CSMR0/DRAM vector problem. 247 */ 248 movel #0x001F0021,%d0 /* disable C/I bit */ 249 movel %d0,0x84(%a0) /* set CSMR0 */ 250 251 /* 252 * Disable the PLL firstly. (Who knows what state it is 253 * in here!). 254 */ 255 movel 0x180(%a1),%d0 /* get current PLL value */ 256 andl #0xfffffffe,%d0 /* PLL bypass first */ 257 movel %d0,0x180(%a1) /* set PLL register */ 258 nop 259 260#if CONFIG_CLOCK_FREQ == 140000000 261 /* 262 * Set initial clock frequency. This assumes M5249C3 board 263 * is fitted with 11.2896MHz crystal. It will program the 264 * PLL for 140MHz. Lets go fast :-) 265 */ 266 movel #0x125a40f0,%d0 /* set for 140MHz */ 267 movel %d0,0x180(%a1) /* set PLL register */ 268 orl #0x1,%d0 269 movel %d0,0x180(%a1) /* set PLL register */ 270#endif 271 272 /* 273 * Setup CS1 for ethernet controller. 274 * (Setup as per M5249C3 doco). 275 */ 276 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */ 277 movel %d0,0x8c(%a0) 278 movel #0x001f0021,%d0 /* CS1 size of 1Mb */ 279 movel %d0,0x90(%a0) 280 movew #0x0080,%d0 /* CS1 = 16bit port, AA */ 281 movew %d0,0x96(%a0) 282 283 /* 284 * Setup CS2 for IDE interface. 285 */ 286 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */ 287 movel %d0,0x98(%a0) 288 movel #0x001f0001,%d0 /* CS2 size of 1MB */ 289 movel %d0,0x9c(%a0) 290 movew #0x0080,%d0 /* CS2 = 16bit, TA */ 291 movew %d0,0xa2(%a0) 292 293 movel #0x00107000,%d0 /* IDEconfig1 */ 294 movel %d0,0x18c(%a1) 295 movel #0x000c0400,%d0 /* IDEconfig2 */ 296 movel %d0,0x190(%a1) 297 298 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */ 299 orl %d0,0xc(%a1) /* function GPIO19 */ 300 orl %d0,0x8(%a1) /* enable GPIO19 as output */ 301 orl %d0,0x4(%a1) /* de-assert IDE reset */ 302.endm 303 304#define PLATFORM_SETUP m5249c3_setup 305 306#endif /* CONFIG_M5249C3 */ 307#endif /* __ASSEMBLER__ */ 308/****************************************************************************/ 309#endif /* m525xsim_h */ 310