18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/****************************************************************************/ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci/* 58c2ecf20Sopenharmony_ci * coldfire.h -- Motorola ColdFire CPU sepecific defines 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com) 88c2ecf20Sopenharmony_ci * (C) Copyright 2000, Lineo (www.lineo.com) 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/****************************************************************************/ 128c2ecf20Sopenharmony_ci#ifndef coldfire_h 138c2ecf20Sopenharmony_ci#define coldfire_h 148c2ecf20Sopenharmony_ci/****************************************************************************/ 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci/* 188c2ecf20Sopenharmony_ci * Define master clock frequency. This is done at config time now. 198c2ecf20Sopenharmony_ci * No point enumerating dozens of possible clock options here. And 208c2ecf20Sopenharmony_ci * in any case new boards come along from time to time that have yet 218c2ecf20Sopenharmony_ci * another different clocking frequency. 228c2ecf20Sopenharmony_ci */ 238c2ecf20Sopenharmony_ci#ifdef CONFIG_CLOCK_FREQ 248c2ecf20Sopenharmony_ci#define MCF_CLK CONFIG_CLOCK_FREQ 258c2ecf20Sopenharmony_ci#else 268c2ecf20Sopenharmony_ci#error "Don't know what your ColdFire CPU clock frequency is??" 278c2ecf20Sopenharmony_ci#endif 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci/* 308c2ecf20Sopenharmony_ci * Define the processor internal peripherals base address. 318c2ecf20Sopenharmony_ci * 328c2ecf20Sopenharmony_ci * The majority of ColdFire parts use an MBAR register to set 338c2ecf20Sopenharmony_ci * the base address. Some have an IPSBAR register instead, and it 348c2ecf20Sopenharmony_ci * has slightly different rules on its size and alignment. Some 358c2ecf20Sopenharmony_ci * parts have fixed addresses and the internal peripherals cannot 368c2ecf20Sopenharmony_ci * be relocated in the CPU address space. 378c2ecf20Sopenharmony_ci * 388c2ecf20Sopenharmony_ci * The value of MBAR or IPSBAR is config time selectable, we no 398c2ecf20Sopenharmony_ci * longer hard define it here. No MBAR or IPSBAR will be defined if 408c2ecf20Sopenharmony_ci * this part has a fixed peripheral address map. 418c2ecf20Sopenharmony_ci */ 428c2ecf20Sopenharmony_ci#ifdef CONFIG_MBAR 438c2ecf20Sopenharmony_ci#define MCF_MBAR CONFIG_MBAR 448c2ecf20Sopenharmony_ci#endif 458c2ecf20Sopenharmony_ci#ifdef CONFIG_IPSBAR 468c2ecf20Sopenharmony_ci#define MCF_IPSBAR CONFIG_IPSBAR 478c2ecf20Sopenharmony_ci#endif 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci/****************************************************************************/ 508c2ecf20Sopenharmony_ci#endif /* coldfire_h */ 51