18c2ecf20Sopenharmony_ci| 28c2ecf20Sopenharmony_ci| x_fline.sa 3.3 1/10/91 38c2ecf20Sopenharmony_ci| 48c2ecf20Sopenharmony_ci| fpsp_fline --- FPSP handler for fline exception 58c2ecf20Sopenharmony_ci| 68c2ecf20Sopenharmony_ci| First determine if the exception is one of the unimplemented 78c2ecf20Sopenharmony_ci| floating point instructions. If so, let fpsp_unimp handle it. 88c2ecf20Sopenharmony_ci| Next, determine if the instruction is an fmovecr with a non-zero 98c2ecf20Sopenharmony_ci| <ea> field. If so, handle here and return. Otherwise, it 108c2ecf20Sopenharmony_ci| must be a real F-line exception. 118c2ecf20Sopenharmony_ci| 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci| Copyright (C) Motorola, Inc. 1990 148c2ecf20Sopenharmony_ci| All Rights Reserved 158c2ecf20Sopenharmony_ci| 168c2ecf20Sopenharmony_ci| For details on the license for this file, please see the 178c2ecf20Sopenharmony_ci| file, README, in this same directory. 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ciX_FLINE: |idnt 2,1 | Motorola 040 Floating Point Software Package 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci |section 8 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_ci#include "fpsp.h" 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci |xref real_fline 268c2ecf20Sopenharmony_ci |xref fpsp_unimp 278c2ecf20Sopenharmony_ci |xref uni_2 288c2ecf20Sopenharmony_ci |xref mem_read 298c2ecf20Sopenharmony_ci |xref fpsp_fmt_error 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci .global fpsp_fline 328c2ecf20Sopenharmony_cifpsp_fline: 338c2ecf20Sopenharmony_ci| 348c2ecf20Sopenharmony_ci| check for unimplemented vector first. Use EXC_VEC-4 because 358c2ecf20Sopenharmony_ci| the equate is valid only after a 'link a6' has pushed one more 368c2ecf20Sopenharmony_ci| long onto the stack. 378c2ecf20Sopenharmony_ci| 388c2ecf20Sopenharmony_ci cmpw #UNIMP_VEC,EXC_VEC-4(%a7) 398c2ecf20Sopenharmony_ci beql fpsp_unimp 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci| 428c2ecf20Sopenharmony_ci| fmovecr with non-zero <ea> handling here 438c2ecf20Sopenharmony_ci| 448c2ecf20Sopenharmony_ci subl #4,%a7 |4 accounts for 2-word difference 458c2ecf20Sopenharmony_ci| ;between six word frame (unimp) and 468c2ecf20Sopenharmony_ci| ;four word frame 478c2ecf20Sopenharmony_ci link %a6,#-LOCAL_SIZE 488c2ecf20Sopenharmony_ci fsave -(%a7) 498c2ecf20Sopenharmony_ci moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 508c2ecf20Sopenharmony_ci moveal EXC_PC+4(%a6),%a0 |get address of fline instruction 518c2ecf20Sopenharmony_ci leal L_SCR1(%a6),%a1 |use L_SCR1 as scratch 528c2ecf20Sopenharmony_ci movel #4,%d0 538c2ecf20Sopenharmony_ci addl #4,%a6 |to offset the sub.l #4,a7 above so that 548c2ecf20Sopenharmony_ci| ;a6 can point correctly to the stack frame 558c2ecf20Sopenharmony_ci| ;before branching to mem_read 568c2ecf20Sopenharmony_ci bsrl mem_read 578c2ecf20Sopenharmony_ci subl #4,%a6 588c2ecf20Sopenharmony_ci movel L_SCR1(%a6),%d0 |d0 contains the fline and command word 598c2ecf20Sopenharmony_ci bfextu %d0{#4:#3},%d1 |extract coprocessor id 608c2ecf20Sopenharmony_ci cmpib #1,%d1 |check if cpid=1 618c2ecf20Sopenharmony_ci bne not_mvcr |exit if not 628c2ecf20Sopenharmony_ci bfextu %d0{#16:#6},%d1 638c2ecf20Sopenharmony_ci cmpib #0x17,%d1 |check if it is an FMOVECR encoding 648c2ecf20Sopenharmony_ci bne not_mvcr 658c2ecf20Sopenharmony_ci| ;if an FMOVECR instruction, fix stack 668c2ecf20Sopenharmony_ci| ;and go to FPSP_UNIMP 678c2ecf20Sopenharmony_cifix_stack: 688c2ecf20Sopenharmony_ci cmpib #VER_40,(%a7) |test for orig unimp frame 698c2ecf20Sopenharmony_ci bnes ck_rev 708c2ecf20Sopenharmony_ci subl #UNIMP_40_SIZE-4,%a7 |emulate an orig fsave 718c2ecf20Sopenharmony_ci moveb #VER_40,(%a7) 728c2ecf20Sopenharmony_ci moveb #UNIMP_40_SIZE-4,1(%a7) 738c2ecf20Sopenharmony_ci clrw 2(%a7) 748c2ecf20Sopenharmony_ci bras fix_con 758c2ecf20Sopenharmony_cick_rev: 768c2ecf20Sopenharmony_ci cmpib #VER_41,(%a7) |test for rev unimp frame 778c2ecf20Sopenharmony_ci bnel fpsp_fmt_error |if not $40 or $41, exit with error 788c2ecf20Sopenharmony_ci subl #UNIMP_41_SIZE-4,%a7 |emulate a rev fsave 798c2ecf20Sopenharmony_ci moveb #VER_41,(%a7) 808c2ecf20Sopenharmony_ci moveb #UNIMP_41_SIZE-4,1(%a7) 818c2ecf20Sopenharmony_ci clrw 2(%a7) 828c2ecf20Sopenharmony_cifix_con: 838c2ecf20Sopenharmony_ci movew EXC_SR+4(%a6),EXC_SR(%a6) |move stacked sr to new position 848c2ecf20Sopenharmony_ci movel EXC_PC+4(%a6),EXC_PC(%a6) |move stacked pc to new position 858c2ecf20Sopenharmony_ci fmovel EXC_PC(%a6),%FPIAR |point FPIAR to fline inst 868c2ecf20Sopenharmony_ci movel #4,%d1 878c2ecf20Sopenharmony_ci addl %d1,EXC_PC(%a6) |increment stacked pc value to next inst 888c2ecf20Sopenharmony_ci movew #0x202c,EXC_VEC(%a6) |reformat vector to unimp 898c2ecf20Sopenharmony_ci clrl EXC_EA(%a6) |clear the EXC_EA field 908c2ecf20Sopenharmony_ci movew %d0,CMDREG1B(%a6) |move the lower word into CMDREG1B 918c2ecf20Sopenharmony_ci clrl E_BYTE(%a6) 928c2ecf20Sopenharmony_ci bsetb #UFLAG,T_BYTE(%a6) 938c2ecf20Sopenharmony_ci moveml USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers 948c2ecf20Sopenharmony_ci bral uni_2 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_cinot_mvcr: 978c2ecf20Sopenharmony_ci moveml USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers 988c2ecf20Sopenharmony_ci frestore (%a7)+ 998c2ecf20Sopenharmony_ci unlk %a6 1008c2ecf20Sopenharmony_ci addl #4,%a7 1018c2ecf20Sopenharmony_ci bral real_fline 1028c2ecf20Sopenharmony_ci 1038c2ecf20Sopenharmony_ci |end 104