18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/***************************************************************************/ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci/* 58c2ecf20Sopenharmony_ci * m54xx.c -- platform support for ColdFire 54xx based boards 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be> 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci/***************************************************************************/ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <linux/kernel.h> 138c2ecf20Sopenharmony_ci#include <linux/param.h> 148c2ecf20Sopenharmony_ci#include <linux/init.h> 158c2ecf20Sopenharmony_ci#include <linux/interrupt.h> 168c2ecf20Sopenharmony_ci#include <linux/io.h> 178c2ecf20Sopenharmony_ci#include <linux/mm.h> 188c2ecf20Sopenharmony_ci#include <linux/clk.h> 198c2ecf20Sopenharmony_ci#include <linux/memblock.h> 208c2ecf20Sopenharmony_ci#include <asm/pgalloc.h> 218c2ecf20Sopenharmony_ci#include <asm/machdep.h> 228c2ecf20Sopenharmony_ci#include <asm/coldfire.h> 238c2ecf20Sopenharmony_ci#include <asm/m54xxsim.h> 248c2ecf20Sopenharmony_ci#include <asm/mcfuart.h> 258c2ecf20Sopenharmony_ci#include <asm/mcfclk.h> 268c2ecf20Sopenharmony_ci#include <asm/m54xxgpt.h> 278c2ecf20Sopenharmony_ci#ifdef CONFIG_MMU 288c2ecf20Sopenharmony_ci#include <asm/mmu_context.h> 298c2ecf20Sopenharmony_ci#endif 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci/***************************************************************************/ 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ciDEFINE_CLK(pll, "pll.0", MCF_CLK); 348c2ecf20Sopenharmony_ciDEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 358c2ecf20Sopenharmony_ciDEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK); 368c2ecf20Sopenharmony_ciDEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK); 378c2ecf20Sopenharmony_ciDEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 388c2ecf20Sopenharmony_ciDEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 398c2ecf20Sopenharmony_ciDEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); 408c2ecf20Sopenharmony_ciDEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK); 418c2ecf20Sopenharmony_ciDEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_cistruct clk *mcf_clks[] = { 448c2ecf20Sopenharmony_ci &clk_pll, 458c2ecf20Sopenharmony_ci &clk_sys, 468c2ecf20Sopenharmony_ci &clk_mcfslt0, 478c2ecf20Sopenharmony_ci &clk_mcfslt1, 488c2ecf20Sopenharmony_ci &clk_mcfuart0, 498c2ecf20Sopenharmony_ci &clk_mcfuart1, 508c2ecf20Sopenharmony_ci &clk_mcfuart2, 518c2ecf20Sopenharmony_ci &clk_mcfuart3, 528c2ecf20Sopenharmony_ci &clk_mcfi2c0, 538c2ecf20Sopenharmony_ci NULL 548c2ecf20Sopenharmony_ci}; 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci/***************************************************************************/ 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_cistatic void __init m54xx_uarts_init(void) 598c2ecf20Sopenharmony_ci{ 608c2ecf20Sopenharmony_ci /* enable io pins */ 618c2ecf20Sopenharmony_ci __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0); 628c2ecf20Sopenharmony_ci __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS, 638c2ecf20Sopenharmony_ci MCFGPIO_PAR_PSC1); 648c2ecf20Sopenharmony_ci __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS | 658c2ecf20Sopenharmony_ci MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2); 668c2ecf20Sopenharmony_ci __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3); 678c2ecf20Sopenharmony_ci} 688c2ecf20Sopenharmony_ci 698c2ecf20Sopenharmony_ci/***************************************************************************/ 708c2ecf20Sopenharmony_ci 718c2ecf20Sopenharmony_cistatic void __init m54xx_i2c_init(void) 728c2ecf20Sopenharmony_ci{ 738c2ecf20Sopenharmony_ci#if IS_ENABLED(CONFIG_I2C_IMX) 748c2ecf20Sopenharmony_ci u32 r; 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci /* set the fec/i2c/irq pin assignment register for i2c */ 778c2ecf20Sopenharmony_ci r = readl(MCF_PAR_FECI2CIRQ); 788c2ecf20Sopenharmony_ci r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL; 798c2ecf20Sopenharmony_ci writel(r, MCF_PAR_FECI2CIRQ); 808c2ecf20Sopenharmony_ci#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ 818c2ecf20Sopenharmony_ci} 828c2ecf20Sopenharmony_ci 838c2ecf20Sopenharmony_ci/***************************************************************************/ 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_cistatic void mcf54xx_reset(void) 868c2ecf20Sopenharmony_ci{ 878c2ecf20Sopenharmony_ci /* disable interrupts and enable the watchdog */ 888c2ecf20Sopenharmony_ci asm("movew #0x2700, %sr\n"); 898c2ecf20Sopenharmony_ci __raw_writel(0, MCF_GPT_GMS0); 908c2ecf20Sopenharmony_ci __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0); 918c2ecf20Sopenharmony_ci __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), 928c2ecf20Sopenharmony_ci MCF_GPT_GMS0); 938c2ecf20Sopenharmony_ci} 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ci/***************************************************************************/ 968c2ecf20Sopenharmony_ci 978c2ecf20Sopenharmony_civoid __init config_BSP(char *commandp, int size) 988c2ecf20Sopenharmony_ci{ 998c2ecf20Sopenharmony_ci mach_reset = mcf54xx_reset; 1008c2ecf20Sopenharmony_ci mach_sched_init = hw_timer_init; 1018c2ecf20Sopenharmony_ci m54xx_uarts_init(); 1028c2ecf20Sopenharmony_ci m54xx_i2c_init(); 1038c2ecf20Sopenharmony_ci} 1048c2ecf20Sopenharmony_ci 1058c2ecf20Sopenharmony_ci/***************************************************************************/ 106