18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/***************************************************************************/ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci/* 58c2ecf20Sopenharmony_ci * 525x.c -- platform support for ColdFire 525x based boards 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Copyright (C) 2012, Steven King <sfking@fdwdc.com> 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci/***************************************************************************/ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <linux/kernel.h> 138c2ecf20Sopenharmony_ci#include <linux/param.h> 148c2ecf20Sopenharmony_ci#include <linux/init.h> 158c2ecf20Sopenharmony_ci#include <linux/io.h> 168c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 178c2ecf20Sopenharmony_ci#include <asm/machdep.h> 188c2ecf20Sopenharmony_ci#include <asm/coldfire.h> 198c2ecf20Sopenharmony_ci#include <asm/mcfsim.h> 208c2ecf20Sopenharmony_ci#include <asm/mcfclk.h> 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci/***************************************************************************/ 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciDEFINE_CLK(pll, "pll.0", MCF_CLK); 258c2ecf20Sopenharmony_ciDEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 268c2ecf20Sopenharmony_ciDEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); 278c2ecf20Sopenharmony_ciDEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); 288c2ecf20Sopenharmony_ciDEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 298c2ecf20Sopenharmony_ciDEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 308c2ecf20Sopenharmony_ciDEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 318c2ecf20Sopenharmony_ciDEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); 328c2ecf20Sopenharmony_ciDEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK); 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_cistruct clk *mcf_clks[] = { 358c2ecf20Sopenharmony_ci &clk_pll, 368c2ecf20Sopenharmony_ci &clk_sys, 378c2ecf20Sopenharmony_ci &clk_mcftmr0, 388c2ecf20Sopenharmony_ci &clk_mcftmr1, 398c2ecf20Sopenharmony_ci &clk_mcfuart0, 408c2ecf20Sopenharmony_ci &clk_mcfuart1, 418c2ecf20Sopenharmony_ci &clk_mcfqspi0, 428c2ecf20Sopenharmony_ci &clk_mcfi2c0, 438c2ecf20Sopenharmony_ci &clk_mcfi2c1, 448c2ecf20Sopenharmony_ci NULL 458c2ecf20Sopenharmony_ci}; 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci/***************************************************************************/ 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_cistatic void __init m525x_qspi_init(void) 508c2ecf20Sopenharmony_ci{ 518c2ecf20Sopenharmony_ci#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 528c2ecf20Sopenharmony_ci /* set the GPIO function for the qspi cs gpios */ 538c2ecf20Sopenharmony_ci /* FIXME: replace with pinmux/pinctl support */ 548c2ecf20Sopenharmony_ci u32 f = readl(MCFSIM2_GPIOFUNC); 558c2ecf20Sopenharmony_ci f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0); 568c2ecf20Sopenharmony_ci writel(f, MCFSIM2_GPIOFUNC); 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ci /* QSPI irq setup */ 598c2ecf20Sopenharmony_ci writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, 608c2ecf20Sopenharmony_ci MCFSIM_QSPIICR); 618c2ecf20Sopenharmony_ci mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); 628c2ecf20Sopenharmony_ci#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 638c2ecf20Sopenharmony_ci} 648c2ecf20Sopenharmony_ci 658c2ecf20Sopenharmony_cistatic void __init m525x_i2c_init(void) 668c2ecf20Sopenharmony_ci{ 678c2ecf20Sopenharmony_ci#if IS_ENABLED(CONFIG_I2C_IMX) 688c2ecf20Sopenharmony_ci u32 r; 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci /* first I2C controller uses regular irq setup */ 718c2ecf20Sopenharmony_ci writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, 728c2ecf20Sopenharmony_ci MCFSIM_I2CICR); 738c2ecf20Sopenharmony_ci mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_ci /* second I2C controller is completely different */ 768c2ecf20Sopenharmony_ci r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); 778c2ecf20Sopenharmony_ci r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1); 788c2ecf20Sopenharmony_ci r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1); 798c2ecf20Sopenharmony_ci writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); 808c2ecf20Sopenharmony_ci#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ 818c2ecf20Sopenharmony_ci} 828c2ecf20Sopenharmony_ci 838c2ecf20Sopenharmony_ci/***************************************************************************/ 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_civoid __init config_BSP(char *commandp, int size) 868c2ecf20Sopenharmony_ci{ 878c2ecf20Sopenharmony_ci mach_sched_init = hw_timer_init; 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_ci m525x_qspi_init(); 908c2ecf20Sopenharmony_ci m525x_i2c_init(); 918c2ecf20Sopenharmony_ci} 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_ci/***************************************************************************/ 94