18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/***************************************************************************/ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci/* 58c2ecf20Sopenharmony_ci * m523x.c -- platform support for ColdFire 523x based boards 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Sub-architcture dependent initialization code for the Freescale 88c2ecf20Sopenharmony_ci * 523x CPUs. 98c2ecf20Sopenharmony_ci * 108c2ecf20Sopenharmony_ci * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com) 118c2ecf20Sopenharmony_ci * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) 128c2ecf20Sopenharmony_ci */ 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci/***************************************************************************/ 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci#include <linux/kernel.h> 178c2ecf20Sopenharmony_ci#include <linux/param.h> 188c2ecf20Sopenharmony_ci#include <linux/init.h> 198c2ecf20Sopenharmony_ci#include <linux/io.h> 208c2ecf20Sopenharmony_ci#include <asm/machdep.h> 218c2ecf20Sopenharmony_ci#include <asm/coldfire.h> 228c2ecf20Sopenharmony_ci#include <asm/mcfsim.h> 238c2ecf20Sopenharmony_ci#include <asm/mcfclk.h> 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci/***************************************************************************/ 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ciDEFINE_CLK(pll, "pll.0", MCF_CLK); 288c2ecf20Sopenharmony_ciDEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 298c2ecf20Sopenharmony_ciDEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); 308c2ecf20Sopenharmony_ciDEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); 318c2ecf20Sopenharmony_ciDEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); 328c2ecf20Sopenharmony_ciDEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); 338c2ecf20Sopenharmony_ciDEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 348c2ecf20Sopenharmony_ciDEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 358c2ecf20Sopenharmony_ciDEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); 368c2ecf20Sopenharmony_ciDEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 378c2ecf20Sopenharmony_ciDEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); 388c2ecf20Sopenharmony_ciDEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); 398c2ecf20Sopenharmony_ci 408c2ecf20Sopenharmony_cistruct clk *mcf_clks[] = { 418c2ecf20Sopenharmony_ci &clk_pll, 428c2ecf20Sopenharmony_ci &clk_sys, 438c2ecf20Sopenharmony_ci &clk_mcfpit0, 448c2ecf20Sopenharmony_ci &clk_mcfpit1, 458c2ecf20Sopenharmony_ci &clk_mcfpit2, 468c2ecf20Sopenharmony_ci &clk_mcfpit3, 478c2ecf20Sopenharmony_ci &clk_mcfuart0, 488c2ecf20Sopenharmony_ci &clk_mcfuart1, 498c2ecf20Sopenharmony_ci &clk_mcfuart2, 508c2ecf20Sopenharmony_ci &clk_mcfqspi0, 518c2ecf20Sopenharmony_ci &clk_fec0, 528c2ecf20Sopenharmony_ci &clk_mcfi2c0, 538c2ecf20Sopenharmony_ci NULL 548c2ecf20Sopenharmony_ci}; 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci/***************************************************************************/ 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_cistatic void __init m523x_qspi_init(void) 598c2ecf20Sopenharmony_ci{ 608c2ecf20Sopenharmony_ci#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 618c2ecf20Sopenharmony_ci u16 par; 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci /* setup QSPS pins for QSPI with gpio CS control */ 648c2ecf20Sopenharmony_ci writeb(0x1f, MCFGPIO_PAR_QSPI); 658c2ecf20Sopenharmony_ci /* and CS2 & CS3 as gpio */ 668c2ecf20Sopenharmony_ci par = readw(MCFGPIO_PAR_TIMER); 678c2ecf20Sopenharmony_ci par &= 0x3f3f; 688c2ecf20Sopenharmony_ci writew(par, MCFGPIO_PAR_TIMER); 698c2ecf20Sopenharmony_ci#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 708c2ecf20Sopenharmony_ci} 718c2ecf20Sopenharmony_ci 728c2ecf20Sopenharmony_ci/***************************************************************************/ 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_cistatic void __init m523x_i2c_init(void) 758c2ecf20Sopenharmony_ci{ 768c2ecf20Sopenharmony_ci#if IS_ENABLED(CONFIG_I2C_IMX) 778c2ecf20Sopenharmony_ci u8 par; 788c2ecf20Sopenharmony_ci 798c2ecf20Sopenharmony_ci /* setup Port AS Pin Assignment Register for I2C */ 808c2ecf20Sopenharmony_ci /* set PASPA0 to SCL and PASPA1 to SDA */ 818c2ecf20Sopenharmony_ci par = readb(MCFGPIO_PAR_FECI2C); 828c2ecf20Sopenharmony_ci par |= 0x0f; 838c2ecf20Sopenharmony_ci writeb(par, MCFGPIO_PAR_FECI2C); 848c2ecf20Sopenharmony_ci#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ 858c2ecf20Sopenharmony_ci} 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_ci/***************************************************************************/ 888c2ecf20Sopenharmony_ci 898c2ecf20Sopenharmony_cistatic void __init m523x_fec_init(void) 908c2ecf20Sopenharmony_ci{ 918c2ecf20Sopenharmony_ci /* Set multi-function pins to ethernet use */ 928c2ecf20Sopenharmony_ci writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C); 938c2ecf20Sopenharmony_ci} 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ci/***************************************************************************/ 968c2ecf20Sopenharmony_ci 978c2ecf20Sopenharmony_civoid __init config_BSP(char *commandp, int size) 988c2ecf20Sopenharmony_ci{ 998c2ecf20Sopenharmony_ci mach_sched_init = hw_timer_init; 1008c2ecf20Sopenharmony_ci m523x_fec_init(); 1018c2ecf20Sopenharmony_ci m523x_qspi_init(); 1028c2ecf20Sopenharmony_ci m523x_i2c_init(); 1038c2ecf20Sopenharmony_ci} 1048c2ecf20Sopenharmony_ci 1058c2ecf20Sopenharmony_ci/***************************************************************************/ 106