1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 2020 Loongson Technology Co., Ltd. 8 */ 9#ifndef _ASM_LOONGARCHREGS_H 10#define _ASM_LOONGARCHREGS_H 11 12#include <linux/bits.h> 13#include <linux/linkage.h> 14#include <linux/types.h> 15 16#ifndef __ASSEMBLY__ 17#include <larchintrin.h> 18 19/* 20 * parse_r var, r - Helper assembler macro for parsing register names. 21 * 22 * This converts the register name in $n form provided in \r to the 23 * corresponding register number, which is assigned to the variable \var. It is 24 * needed to allow explicit encoding of instructions in inline assembly where 25 * registers are chosen by the compiler in $n form, allowing us to avoid using 26 * fixed register numbers. 27 * 28 * It also allows newer instructions (not implemented by the assembler) to be 29 * transparently implemented using assembler macros, instead of needing separate 30 * cases depending on toolchain support. 31 * 32 * Simple usage example: 33 * __asm__ __volatile__("parse_r __rt, %0\n\t" 34 * "# di %0\n\t" 35 * ".word (0x41606000 | (__rt << 16))" 36 * : "=r" (status); 37 */ 38 39/* Match an individual register number and assign to \var */ 40#define _IFC_REG(n) \ 41 ".ifc \\r, $r" #n "\n\t" \ 42 "\\var = " #n "\n\t" \ 43 ".endif\n\t" 44 45__asm__(".macro parse_r var r\n\t" 46 "\\var = -1\n\t" 47 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) 48 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) 49 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) 50 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) 51 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) 52 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) 53 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) 54 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) 55 ".iflt \\var\n\t" 56 ".error \"Unable to parse register name \\r\"\n\t" 57 ".endif\n\t" 58 ".endm"); 59 60#undef _IFC_REG 61 62/* CPUCFG */ 63#define read_cpucfg(reg) __cpucfg(reg) 64 65#endif /* !__ASSEMBLY__ */ 66 67/* LoongArch Registers */ 68#define REG_ZERO 0x0 69#define REG_RA 0x1 70#define REG_TP 0x2 71#define REG_SP 0x3 72#define REG_A0 0x4 /* Reused as V0 for return value */ 73#define REG_A1 0x5 /* Reused as V1 for return value */ 74#define REG_A2 0x6 75#define REG_A3 0x7 76#define REG_A4 0x8 77#define REG_A5 0x9 78#define REG_A6 0xa 79#define REG_A7 0xb 80#define REG_T0 0xc 81#define REG_T1 0xd 82#define REG_T2 0xe 83#define REG_T3 0xf 84#define REG_T4 0x10 85#define REG_T5 0x11 86#define REG_T6 0x12 87#define REG_T7 0x13 88#define REG_T8 0x14 89#define REG_U0 0x15 /* Kernel uses it as percpu base */ 90#define REG_FP 0x16 91#define REG_S0 0x17 92#define REG_S1 0x18 93#define REG_S2 0x19 94#define REG_S3 0x1a 95#define REG_S4 0x1b 96#define REG_S5 0x1c 97#define REG_S6 0x1d 98#define REG_S7 0x1e 99#define REG_S8 0x1f 100 101/* Bit fields for CPUCFG registers */ 102#define LOONGARCH_CPUCFG0 0x0 103#define CPUCFG0_PRID GENMASK(31, 0) 104 105#define LOONGARCH_CPUCFG1 0x1 106#define CPUCFG1_ISGR32 BIT(0) 107#define CPUCFG1_ISGR64 BIT(1) 108#define CPUCFG1_PAGING BIT(2) 109#define CPUCFG1_IOCSR BIT(3) 110#define CPUCFG1_PABITS GENMASK(11, 4) 111#define CPUCFG1_VABITS GENMASK(19, 12) 112#define CPUCFG1_UAL BIT(20) 113#define CPUCFG1_RI BIT(21) 114#define CPUCFG1_EP BIT(22) 115#define CPUCFG1_RPLV BIT(23) 116#define CPUCFG1_HUGEPG BIT(24) 117#define CPUCFG1_CRC32 BIT(25) 118#define CPUCFG1_MSGINT BIT(26) 119 120#define LOONGARCH_CPUCFG2 0x2 121#define CPUCFG2_FP BIT(0) 122#define CPUCFG2_FPSP BIT(1) 123#define CPUCFG2_FPDP BIT(2) 124#define CPUCFG2_FPVERS GENMASK(5, 3) 125#define CPUCFG2_LSX BIT(6) 126#define CPUCFG2_LASX BIT(7) 127#define CPUCFG2_COMPLEX BIT(8) 128#define CPUCFG2_CRYPTO BIT(9) 129#define CPUCFG2_LVZP BIT(10) 130#define CPUCFG2_LVZVER GENMASK(13, 11) 131#define CPUCFG2_LLFTP BIT(14) 132#define CPUCFG2_LLFTPREV GENMASK(17, 15) 133#define CPUCFG2_X86BT BIT(18) 134#define CPUCFG2_ARMBT BIT(19) 135#define CPUCFG2_MIPSBT BIT(20) 136#define CPUCFG2_LSPW BIT(21) 137#define CPUCFG2_LAM BIT(22) 138#define CPUCFG2_PTW BIT(24) 139 140#define LOONGARCH_CPUCFG3 0x3 141#define CPUCFG3_CCDMA BIT(0) 142#define CPUCFG3_SFB BIT(1) 143#define CPUCFG3_UCACC BIT(2) 144#define CPUCFG3_LLEXC BIT(3) 145#define CPUCFG3_SCDLY BIT(4) 146#define CPUCFG3_LLDBAR BIT(5) 147#define CPUCFG3_ITLBT BIT(6) 148#define CPUCFG3_ICACHET BIT(7) 149#define CPUCFG3_SPW_LVL GENMASK(10, 8) 150#define CPUCFG3_SPW_HG_HF BIT(11) 151#define CPUCFG3_RVA BIT(12) 152#define CPUCFG3_RVAMAX GENMASK(16, 13) 153 154#define LOONGARCH_CPUCFG4 0x4 155#define CPUCFG4_CCFREQ GENMASK(31, 0) 156 157#define LOONGARCH_CPUCFG5 0x5 158#define CPUCFG5_CCMUL GENMASK(15, 0) 159#define CPUCFG5_CCDIV GENMASK(31, 16) 160 161#define LOONGARCH_CPUCFG6 0x6 162#define CPUCFG6_PMP BIT(0) 163#define CPUCFG6_PAMVER GENMASK(3, 1) 164#define CPUCFG6_PMNUM GENMASK(7, 4) 165#define CPUCFG6_PMBITS GENMASK(13, 8) 166#define CPUCFG6_UPM BIT(14) 167 168#define LOONGARCH_CPUCFG16 0x10 169#define CPUCFG16_L1_IUPRE BIT(0) 170#define CPUCFG16_L1_IUUNIFY BIT(1) 171#define CPUCFG16_L1_DPRE BIT(2) 172#define CPUCFG16_L2_IUPRE BIT(3) 173#define CPUCFG16_L2_IUUNIFY BIT(4) 174#define CPUCFG16_L2_IUPRIV BIT(5) 175#define CPUCFG16_L2_IUINCL BIT(6) 176#define CPUCFG16_L2_DPRE BIT(7) 177#define CPUCFG16_L2_DPRIV BIT(8) 178#define CPUCFG16_L2_DINCL BIT(9) 179#define CPUCFG16_L3_IUPRE BIT(10) 180#define CPUCFG16_L3_IUUNIFY BIT(11) 181#define CPUCFG16_L3_IUPRIV BIT(12) 182#define CPUCFG16_L3_IUINCL BIT(13) 183#define CPUCFG16_L3_DPRE BIT(14) 184#define CPUCFG16_L3_DPRIV BIT(15) 185#define CPUCFG16_L3_DINCL BIT(16) 186 187#define LOONGARCH_CPUCFG17 0x11 188#define LOONGARCH_CPUCFG18 0x12 189#define LOONGARCH_CPUCFG19 0x13 190#define LOONGARCH_CPUCFG20 0x14 191#define CPUCFG_CACHE_WAYS_M GENMASK(15, 0) 192#define CPUCFG_CACHE_SETS_M GENMASK(23, 16) 193#define CPUCFG_CACHE_LSIZE_M GENMASK(30, 24) 194#define CPUCFG_CACHE_WAYS 0 195#define CPUCFG_CACHE_SETS 16 196#define CPUCFG_CACHE_LSIZE 24 197 198#define LOONGARCH_CPUCFG48 0x30 199#define CPUCFG48_MCSR_LCK BIT(0) 200#define CPUCFG48_NAP_EN BIT(1) 201#define CPUCFG48_VFPU_CG BIT(2) 202#define CPUCFG48_RAM_CG BIT(3) 203 204#ifndef __ASSEMBLY__ 205 206/* CSR */ 207#define csr_read32(reg) __csrrd_w(reg) 208#define csr_read64(reg) __csrrd_d(reg) 209#define csr_write32(val, reg) __csrwr_w(val, reg) 210#define csr_write64(val, reg) __csrwr_d(val, reg) 211#define csr_xchg32(val, mask, reg) __csrxchg_w(val, mask, reg) 212#define csr_xchg64(val, mask, reg) __csrxchg_d(val, mask, reg) 213 214/* IOCSR */ 215#define iocsr_read32(reg) __iocsrrd_w(reg) 216#define iocsr_read64(reg) __iocsrrd_d(reg) 217#define iocsr_write8(val, reg) __iocsrwr_b(val, reg) 218#define iocsr_write32(val, reg) __iocsrwr_w(val, reg) 219#define iocsr_write64(val, reg) __iocsrwr_d(val, reg) 220 221/* GCSR */ 222#define gcsr_read(csr) \ 223({ \ 224 register unsigned long __v = 0; \ 225 __asm__ __volatile__ ( \ 226 "parse_r __reg, %[val] \n\t" \ 227 ".word 0x5 << 24 | %[reg] << 10 | 0 << 5 | __reg \n\t" \ 228 : [val] "+r" (__v) \ 229 : [reg] "i" (csr) \ 230 : "memory"); \ 231 __v; \ 232}) 233 234#define gcsr_write(v, csr) \ 235({ \ 236 register unsigned long __v = v; \ 237 __asm__ __volatile__ ( \ 238 "parse_r __reg, %[val] \n\t" \ 239 ".word 0x5 << 24 | %[reg] << 10 | 1 << 5 | __reg \n\t" \ 240 : [val] "+r" (__v) \ 241 : [reg] "i" (csr) \ 242 : "memory"); \ 243}) 244 245#define gcsr_xchg(v, m, csr) \ 246({ \ 247 register unsigned long __v = v; \ 248 __asm__ __volatile__ ( \ 249 "parse_r __rd, %[val] \n\t" \ 250 "parse_r __rj, %[mask] \n\t" \ 251 ".word 0x5 << 24 | %[reg] << 10 | __rj << 5 | __rd \n\t" \ 252 : [val] "+r" (__v) \ 253 : [mask] "r" (m), [reg] "i" (csr) \ 254 : "memory"); \ 255 __v; \ 256}) 257 258#endif /* !__ASSEMBLY__ */ 259 260/* CSR register number */ 261 262/* Basic CSR registers */ 263#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */ 264#define CSR_CRMD_WE_SHIFT 9 265#define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT) 266#define CSR_CRMD_DACM_SHIFT 7 267#define CSR_CRMD_DACM_WIDTH 2 268#define CSR_CRMD_DACM (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT) 269#define CSR_CRMD_DACF_SHIFT 5 270#define CSR_CRMD_DACF_WIDTH 2 271#define CSR_CRMD_DACF (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT) 272#define CSR_CRMD_PG_SHIFT 4 273#define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT) 274#define CSR_CRMD_DA_SHIFT 3 275#define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT) 276#define CSR_CRMD_IE_SHIFT 2 277#define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT) 278#define CSR_CRMD_PLV_SHIFT 0 279#define CSR_CRMD_PLV_WIDTH 2 280#define CSR_CRMD_PLV (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT) 281 282#define PLV_KERN 0 283#define PLV_USER 3 284#define PLV_MASK 0x3 285 286#define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */ 287#define CSR_PRMD_PWE_SHIFT 3 288#define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT) 289#define CSR_PRMD_PIE_SHIFT 2 290#define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT) 291#define CSR_PRMD_PPLV_SHIFT 0 292#define CSR_PRMD_PPLV_WIDTH 2 293#define CSR_PRMD_PPLV (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT) 294 295#define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */ 296#define CSR_EUEN_LBTEN_SHIFT 3 297#define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT) 298#define CSR_EUEN_LASXEN_SHIFT 2 299#define CSR_EUEN_LASXEN (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT) 300#define CSR_EUEN_LSXEN_SHIFT 1 301#define CSR_EUEN_LSXEN (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT) 302#define CSR_EUEN_FPEN_SHIFT 0 303#define CSR_EUEN_FPEN (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT) 304 305#define LOONGARCH_CSR_MISC 0x3 /* Misc config */ 306 307#define LOONGARCH_CSR_ECFG 0x4 /* Exception config */ 308#define CSR_ECFG_VS_SHIFT 16 309#define CSR_ECFG_VS_WIDTH 3 310#define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT) 311#define CSR_ECFG_IM_SHIFT 0 312#define CSR_ECFG_IM_WIDTH 14 313#define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT) 314 315#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ 316#define CSR_ESTAT_ESUBCODE_SHIFT 22 317#define CSR_ESTAT_ESUBCODE_WIDTH 9 318#define CSR_ESTAT_ESUBCODE (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT) 319#define CSR_ESTAT_EXC_SHIFT 16 320#define CSR_ESTAT_EXC_WIDTH 6 321#define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT) 322#define CSR_ESTAT_IS_SHIFT 0 323#define CSR_ESTAT_IS_WIDTH 14 324#define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT) 325 326#define LOONGARCH_CSR_ERA 0x6 /* ERA */ 327 328#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */ 329 330#define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */ 331 332#define LOONGARCH_CSR_EENTRY 0xc /* Exception entry */ 333 334/* TLB related CSR registers */ 335#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */ 336#define CSR_TLBIDX_EHINV_SHIFT 31 337#define CSR_TLBIDX_EHINV (_ULCAST_(1) << CSR_TLBIDX_EHINV_SHIFT) 338#define CSR_TLBIDX_PS_SHIFT 24 339#define CSR_TLBIDX_PS_WIDTH 6 340#define CSR_TLBIDX_PS (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT) 341#define CSR_TLBIDX_IDX_SHIFT 0 342#define CSR_TLBIDX_IDX_WIDTH 12 343#define CSR_TLBIDX_IDX (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT) 344#define CSR_TLBIDX_SIZEM 0x3f000000 345#define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT 346#define CSR_TLBIDX_IDXM 0xfff 347#define CSR_INVALID_ENTRY(e) (CSR_TLBIDX_EHINV | e) 348 349#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */ 350 351#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */ 352#define CSR_TLBLO0_RPLV_SHIFT 63 353#define CSR_TLBLO0_RPLV (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT) 354#define CSR_TLBLO0_NX_SHIFT 62 355#define CSR_TLBLO0_NX (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT) 356#define CSR_TLBLO0_NR_SHIFT 61 357#define CSR_TLBLO0_NR (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT) 358#define CSR_TLBLO0_PFN_SHIFT 12 359#define CSR_TLBLO0_PFN_WIDTH 36 360#define CSR_TLBLO0_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT) 361#define CSR_TLBLO0_GLOBAL_SHIFT 6 362#define CSR_TLBLO0_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT) 363#define CSR_TLBLO0_CCA_SHIFT 4 364#define CSR_TLBLO0_CCA_WIDTH 2 365#define CSR_TLBLO0_CCA (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT) 366#define CSR_TLBLO0_PLV_SHIFT 2 367#define CSR_TLBLO0_PLV_WIDTH 2 368#define CSR_TLBLO0_PLV (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT) 369#define CSR_TLBLO0_WE_SHIFT 1 370#define CSR_TLBLO0_WE (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT) 371#define CSR_TLBLO0_V_SHIFT 0 372#define CSR_TLBLO0_V (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT) 373 374#define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */ 375#define CSR_TLBLO1_RPLV_SHIFT 63 376#define CSR_TLBLO1_RPLV (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT) 377#define CSR_TLBLO1_NX_SHIFT 62 378#define CSR_TLBLO1_NX (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT) 379#define CSR_TLBLO1_NR_SHIFT 61 380#define CSR_TLBLO1_NR (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT) 381#define CSR_TLBLO1_PFN_SHIFT 12 382#define CSR_TLBLO1_PFN_WIDTH 36 383#define CSR_TLBLO1_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT) 384#define CSR_TLBLO1_GLOBAL_SHIFT 6 385#define CSR_TLBLO1_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT) 386#define CSR_TLBLO1_CCA_SHIFT 4 387#define CSR_TLBLO1_CCA_WIDTH 2 388#define CSR_TLBLO1_CCA (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT) 389#define CSR_TLBLO1_PLV_SHIFT 2 390#define CSR_TLBLO1_PLV_WIDTH 2 391#define CSR_TLBLO1_PLV (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT) 392#define CSR_TLBLO1_WE_SHIFT 1 393#define CSR_TLBLO1_WE (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT) 394#define CSR_TLBLO1_V_SHIFT 0 395#define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT) 396 397#define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */ 398#define CSR_GTLBC_TGID_SHIFT 16 399#define CSR_GTLBC_TGID_WIDTH 8 400#define CSR_GTLBC_TGID (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT) 401#define CSR_GTLBC_TOTI_SHIFT 13 402#define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT) 403#define CSR_GTLBC_USETGID_SHIFT 12 404#define CSR_GTLBC_USETGID (_ULCAST_(0x1) << CSR_GTLBC_USETGID_SHIFT) 405#define CSR_GTLBC_GMTLBSZ_SHIFT 0 406#define CSR_GTLBC_GMTLBSZ_WIDTH 6 407#define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT) 408 409#define LOONGARCH_CSR_TRGP 0x16 /* TLBR read guest info */ 410#define CSR_TRGP_RID_SHIFT 16 411#define CSR_TRGP_RID_WIDTH 8 412#define CSR_TRGP_RID (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT) 413#define CSR_TRGP_GTLB_SHIFT 0 414#define CSR_TRGP_GTLB (1 << CSR_TRGP_GTLB_SHIFT) 415 416#define LOONGARCH_CSR_ASID 0x18 /* ASID */ 417#define CSR_ASID_BIT_SHIFT 16 /* ASIDBits */ 418#define CSR_ASID_BIT_WIDTH 8 419#define CSR_ASID_BIT (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT) 420#define CSR_ASID_ASID_SHIFT 0 421#define CSR_ASID_ASID_WIDTH 10 422#define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT) 423 424#define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[VALEN-1] = 0 */ 425 426#define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[VALEN-1] = 1 */ 427 428#define LOONGARCH_CSR_PGD 0x1b /* Page table base */ 429 430#define LOONGARCH_CSR_PWCTL0 0x1c /* PWCtl0 */ 431#define CSR_PWCTL0_PTEW_SHIFT 30 432#define CSR_PWCTL0_PTEW_WIDTH 2 433#define CSR_PWCTL0_PTEW (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT) 434#define CSR_PWCTL0_DIR1WIDTH_SHIFT 25 435#define CSR_PWCTL0_DIR1WIDTH_WIDTH 5 436#define CSR_PWCTL0_DIR1WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT) 437#define CSR_PWCTL0_DIR1BASE_SHIFT 20 438#define CSR_PWCTL0_DIR1BASE_WIDTH 5 439#define CSR_PWCTL0_DIR1BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT) 440#define CSR_PWCTL0_DIR0WIDTH_SHIFT 15 441#define CSR_PWCTL0_DIR0WIDTH_WIDTH 5 442#define CSR_PWCTL0_DIR0WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT) 443#define CSR_PWCTL0_DIR0BASE_SHIFT 10 444#define CSR_PWCTL0_DIR0BASE_WIDTH 5 445#define CSR_PWCTL0_DIR0BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT) 446#define CSR_PWCTL0_PTWIDTH_SHIFT 5 447#define CSR_PWCTL0_PTWIDTH_WIDTH 5 448#define CSR_PWCTL0_PTWIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT) 449#define CSR_PWCTL0_PTBASE_SHIFT 0 450#define CSR_PWCTL0_PTBASE_WIDTH 5 451#define CSR_PWCTL0_PTBASE (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT) 452 453#define LOONGARCH_CSR_PWCTL1 0x1d /* PWCtl1 */ 454#define CSR_PWCTL1_PTW_SHIFT 24 455#define CSR_PWCTL1_PTW_WIDTH 1 456#define CSR_PWCTL1_PTW (_ULCAST_(0x1) << CSR_PWCTL1_PTW_SHIFT) 457#define CSR_PWCTL1_DIR3WIDTH_SHIFT 18 458#define CSR_PWCTL1_DIR3WIDTH_WIDTH 5 459#define CSR_PWCTL1_DIR3WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT) 460#define CSR_PWCTL1_DIR3BASE_SHIFT 12 461#define CSR_PWCTL1_DIR3BASE_WIDTH 5 462#define CSR_PWCTL1_DIR3BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT) 463#define CSR_PWCTL1_DIR2WIDTH_SHIFT 6 464#define CSR_PWCTL1_DIR2WIDTH_WIDTH 5 465#define CSR_PWCTL1_DIR2WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT) 466#define CSR_PWCTL1_DIR2BASE_SHIFT 0 467#define CSR_PWCTL1_DIR2BASE_WIDTH 5 468#define CSR_PWCTL1_DIR2BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT) 469 470#define LOONGARCH_CSR_STLBPGSIZE 0x1e 471#define CSR_STLBPGSIZE_PS_WIDTH 6 472#define CSR_STLBPGSIZE_PS (_ULCAST_(0x3f)) 473 474#define LOONGARCH_CSR_RVACFG 0x1f 475#define CSR_RVACFG_RDVA_WIDTH 4 476#define CSR_RVACFG_RDVA (_ULCAST_(0xf)) 477 478/* Config CSR registers */ 479#define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */ 480#define CSR_CPUID_COREID_WIDTH 9 481#define CSR_CPUID_COREID _ULCAST_(0x1ff) 482 483#define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */ 484#define CSR_CONF1_VSMAX_SHIFT 12 485#define CSR_CONF1_VSMAX_WIDTH 3 486#define CSR_CONF1_VSMAX (_ULCAST_(7) << CSR_CONF1_VSMAX_SHIFT) 487#define CSR_CONF1_TMRBITS_SHIFT 4 488#define CSR_CONF1_TMRBITS_WIDTH 8 489#define CSR_CONF1_TMRBITS (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT) 490#define CSR_CONF1_KSNUM_WIDTH 4 491#define CSR_CONF1_KSNUM _ULCAST_(0xf) 492 493#define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */ 494#define CSR_CONF2_PGMASK_SUPP 0x3ffff000 495 496#define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */ 497#define CSR_CONF3_STLBIDX_SHIFT 20 498#define CSR_CONF3_STLBIDX_WIDTH 6 499#define CSR_CONF3_STLBIDX (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT) 500#define CSR_CONF3_STLBWAYS_SHIFT 12 501#define CSR_CONF3_STLBWAYS_WIDTH 8 502#define CSR_CONF3_STLBWAYS (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT) 503#define CSR_CONF3_MTLBSIZE_SHIFT 4 504#define CSR_CONF3_MTLBSIZE_WIDTH 8 505#define CSR_CONF3_MTLBSIZE (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT) 506#define CSR_CONF3_TLBTYPE_SHIFT 0 507#define CSR_CONF3_TLBTYPE_WIDTH 4 508#define CSR_CONF3_TLBTYPE (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT) 509 510/* KSave registers */ 511#define LOONGARCH_CSR_KS0 0x30 512#define LOONGARCH_CSR_KS1 0x31 513#define LOONGARCH_CSR_KS2 0x32 514#define LOONGARCH_CSR_KS3 0x33 515#define LOONGARCH_CSR_KS4 0x34 516#define LOONGARCH_CSR_KS5 0x35 517#define LOONGARCH_CSR_KS6 0x36 518#define LOONGARCH_CSR_KS7 0x37 519#define LOONGARCH_CSR_KS8 0x38 520 521/* Exception allocated KS0, KS1 and KS2 statically */ 522#define EXCEPTION_KS0 LOONGARCH_CSR_KS0 523#define EXCEPTION_KS1 LOONGARCH_CSR_KS1 524#define EXCEPTION_KS2 LOONGARCH_CSR_KS2 525#define EXC_KSAVE_MASK (1 << 0 | 1 << 1 | 1 << 2) 526 527/* Percpu-data base allocated KS3 statically */ 528#define PERCPU_BASE_KS LOONGARCH_CSR_KS3 529#define PERCPU_KSAVE_MASK (1 << 3) 530 531/* KVM allocated KS4 and KS5 statically */ 532#define KVM_VCPU_KS LOONGARCH_CSR_KS4 533#define KVM_TEMP_KS LOONGARCH_CSR_KS5 534#define KVM_KSAVE_MASK (1 << 4 | 1 << 5) 535 536/* Timer registers */ 537#define LOONGARCH_CSR_TMID 0x40 /* Timer ID */ 538 539#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */ 540#define CSR_TCFG_VAL_SHIFT 2 541#define CSR_TCFG_VAL_WIDTH 48 542#define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT) 543#define CSR_TCFG_PERIOD_SHIFT 1 544#define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT) 545#define CSR_TCFG_EN (_ULCAST_(0x1)) 546 547#define LOONGARCH_CSR_TVAL 0x42 /* Timer value */ 548 549#define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */ 550 551#define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */ 552#define CSR_TINTCLR_TI_SHIFT 0 553#define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT) 554 555/* Guest registers */ 556#define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */ 557#define CSR_GSTAT_GID_SHIFT 16 558#define CSR_GSTAT_GID_WIDTH 8 559#define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT) 560#define CSR_GSTAT_GIDBIT_SHIFT 4 561#define CSR_GSTAT_GIDBIT_WIDTH 6 562#define CSR_GSTAT_GIDBIT (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT) 563#define CSR_GSTAT_PVM_SHIFT 1 564#define CSR_GSTAT_PVM (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT) 565#define CSR_GSTAT_VM_SHIFT 0 566#define CSR_GSTAT_VM (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT) 567 568#define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ 569#define CSR_GCFG_GPERF_SHIFT 24 570#define CSR_GCFG_GPERF_WIDTH 3 571#define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) 572#define CSR_GCFG_GCI_SHIFT 20 573#define CSR_GCFG_GCI_WIDTH 2 574#define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) 575#define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) 576#define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) 577#define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) 578#define CSR_GCFG_GCIP_SHIFT 16 579#define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) 580#define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) 581#define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) 582#define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) 583#define CSR_GCFG_TORU_SHIFT 15 584#define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) 585#define CSR_GCFG_TORUP_SHIFT 14 586#define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) 587#define CSR_GCFG_TOP_SHIFT 13 588#define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) 589#define CSR_GCFG_TOPP_SHIFT 12 590#define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) 591#define CSR_GCFG_TOE_SHIFT 11 592#define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) 593#define CSR_GCFG_TOEP_SHIFT 10 594#define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) 595#define CSR_GCFG_TIT_SHIFT 9 596#define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) 597#define CSR_GCFG_TITP_SHIFT 8 598#define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) 599#define CSR_GCFG_SIT_SHIFT 7 600#define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) 601#define CSR_GCFG_SITP_SHIFT 6 602#define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) 603#define CSR_GCFG_MATC_SHITF 4 604#define CSR_GCFG_MATC_WIDTH 2 605#define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) 606#define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) 607#define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) 608#define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) 609#define CSR_GCFG_MATP_SHITF 0 610#define CSR_GCFG_MATP_WIDTH 4 611#define CSR_GCFG_MATP_MASK (_ULCAST_(0x3) << CSR_GCFG_MATP_SHITF) 612#define CSR_GCFG_MATP_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATP_SHITF) 613#define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_SHITF) 614#define CSR_GCFG_MATP_NEST (_ULCAST_(0x2) << CSR_GCFG_MATP_SHITF) 615 616#define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ 617#define CSR_GINTC_HC_SHIFT 16 618#define CSR_GINTC_HC_WIDTH 8 619#define CSR_GINTC_HC (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT) 620#define CSR_GINTC_PIP_SHIFT 8 621#define CSR_GINTC_PIP_WIDTH 8 622#define CSR_GINTC_PIP (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT) 623#define CSR_GINTC_VIP_SHIFT 0 624#define CSR_GINTC_VIP_WIDTH 8 625#define CSR_GINTC_VIP (_ULCAST_(0xff)) 626 627#define LOONGARCH_CSR_GCNTC 0x53 /* Guest timer offset */ 628 629/* LLBCTL register */ 630#define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */ 631#define CSR_LLBCTL_ROLLB_SHIFT 0 632#define CSR_LLBCTL_ROLLB (_ULCAST_(1) << CSR_LLBCTL_ROLLB_SHIFT) 633#define CSR_LLBCTL_WCLLB_SHIFT 1 634#define CSR_LLBCTL_WCLLB (_ULCAST_(1) << CSR_LLBCTL_WCLLB_SHIFT) 635#define CSR_LLBCTL_KLO_SHIFT 2 636#define CSR_LLBCTL_KLO (_ULCAST_(1) << CSR_LLBCTL_KLO_SHIFT) 637 638/* Implement dependent */ 639#define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */ 640#define CSR_MISPEC_SHIFT 20 641#define CSR_MISPEC_WIDTH 8 642#define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT) 643#define CSR_SSEN_SHIFT 18 644#define CSR_SSEN (_ULCAST_(1) << CSR_SSEN_SHIFT) 645#define CSR_SCRAND_SHIFT 17 646#define CSR_SCRAND (_ULCAST_(1) << CSR_SCRAND_SHIFT) 647#define CSR_LLEXCL_SHIFT 16 648#define CSR_LLEXCL (_ULCAST_(1) << CSR_LLEXCL_SHIFT) 649#define CSR_DISVC_SHIFT 15 650#define CSR_DISVC (_ULCAST_(1) << CSR_DISVC_SHIFT) 651#define CSR_VCLRU_SHIFT 14 652#define CSR_VCLRU (_ULCAST_(1) << CSR_VCLRU_SHIFT) 653#define CSR_DCLRU_SHIFT 13 654#define CSR_DCLRU (_ULCAST_(1) << CSR_DCLRU_SHIFT) 655#define CSR_FASTLDQ_SHIFT 12 656#define CSR_FASTLDQ (_ULCAST_(1) << CSR_FASTLDQ_SHIFT) 657#define CSR_USERCAC_SHIFT 11 658#define CSR_USERCAC (_ULCAST_(1) << CSR_USERCAC_SHIFT) 659#define CSR_ANTI_MISPEC_SHIFT 10 660#define CSR_ANTI_MISPEC (_ULCAST_(1) << CSR_ANTI_MISPEC_SHIFT) 661#define CSR_AUTO_FLUSHSFB_SHIFT 9 662#define CSR_AUTO_FLUSHSFB (_ULCAST_(1) << CSR_AUTO_FLUSHSFB_SHIFT) 663#define CSR_STFILL_SHIFT 8 664#define CSR_STFILL (_ULCAST_(1) << CSR_STFILL_SHIFT) 665#define CSR_LIFEP_SHIFT 7 666#define CSR_LIFEP (_ULCAST_(1) << CSR_LIFEP_SHIFT) 667#define CSR_LLSYNC_SHIFT 6 668#define CSR_LLSYNC (_ULCAST_(1) << CSR_LLSYNC_SHIFT) 669#define CSR_BRBTDIS_SHIFT 5 670#define CSR_BRBTDIS (_ULCAST_(1) << CSR_BRBTDIS_SHIFT) 671#define CSR_RASDIS_SHIFT 4 672#define CSR_RASDIS (_ULCAST_(1) << CSR_RASDIS_SHIFT) 673#define CSR_STPRE_SHIFT 2 674#define CSR_STPRE_WIDTH 2 675#define CSR_STPRE (_ULCAST_(3) << CSR_STPRE_SHIFT) 676#define CSR_INSTPRE_SHIFT 1 677#define CSR_INSTPRE (_ULCAST_(1) << CSR_INSTPRE_SHIFT) 678#define CSR_DATAPRE_SHIFT 0 679#define CSR_DATAPRE (_ULCAST_(1) << CSR_DATAPRE_SHIFT) 680 681#define LOONGARCH_CSR_IMPCTL2 0x81 /* Loongson config2 */ 682#define CSR_FLUSH_MTLB_SHIFT 0 683#define CSR_FLUSH_MTLB (_ULCAST_(1) << CSR_FLUSH_MTLB_SHIFT) 684#define CSR_FLUSH_STLB_SHIFT 1 685#define CSR_FLUSH_STLB (_ULCAST_(1) << CSR_FLUSH_STLB_SHIFT) 686#define CSR_FLUSH_DTLB_SHIFT 2 687#define CSR_FLUSH_DTLB (_ULCAST_(1) << CSR_FLUSH_DTLB_SHIFT) 688#define CSR_FLUSH_ITLB_SHIFT 3 689#define CSR_FLUSH_ITLB (_ULCAST_(1) << CSR_FLUSH_ITLB_SHIFT) 690#define CSR_FLUSH_BTAC_SHIFT 4 691#define CSR_FLUSH_BTAC (_ULCAST_(1) << CSR_FLUSH_BTAC_SHIFT) 692 693#define LOONGARCH_CSR_GNMI 0x82 694 695/* TLB Refill registers */ 696#define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception entry */ 697#define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */ 698#define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */ 699#define LOONGARCH_CSR_TLBRSAVE 0x8b /* KSave for TLB refill exception */ 700#define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */ 701#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */ 702#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */ 703#define CSR_TLBREHI_PS_SHIFT 0 704#define CSR_TLBREHI_PS (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT) 705#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */ 706 707/* Machine Error registers */ 708#define LOONGARCH_CSR_MERRCTL 0x90 /* MERRCTL */ 709#define LOONGARCH_CSR_MERRINFO1 0x91 /* MError info1 */ 710#define LOONGARCH_CSR_MERRINFO2 0x92 /* MError info2 */ 711#define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception entry */ 712#define LOONGARCH_CSR_MERRERA 0x94 /* MError exception ERA */ 713#define LOONGARCH_CSR_MERRSAVE 0x95 /* KSave for machine error exception */ 714 715#define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */ 716 717#define LOONGARCH_CSR_PRID 0xc0 718 719/* Shadow MCSR : 0xc0 ~ 0xff */ 720#define LOONGARCH_CSR_MCSR0 0xc0 /* CPUCFG0 and CPUCFG1 */ 721#define MCSR0_INT_IMPL_SHIFT 58 722#define MCSR0_INT_IMPL 0 723#define MCSR0_IOCSR_BRD_SHIFT 57 724#define MCSR0_IOCSR_BRD (_ULCAST_(1) << MCSR0_IOCSR_BRD_SHIFT) 725#define MCSR0_HUGEPG_SHIFT 56 726#define MCSR0_HUGEPG (_ULCAST_(1) << MCSR0_HUGEPG_SHIFT) 727#define MCSR0_RPLMTLB_SHIFT 55 728#define MCSR0_RPLMTLB (_ULCAST_(1) << MCSR0_RPLMTLB_SHIFT) 729#define MCSR0_EP_SHIFT 54 730#define MCSR0_EP (_ULCAST_(1) << MCSR0_EP_SHIFT) 731#define MCSR0_RI_SHIFT 53 732#define MCSR0_RI (_ULCAST_(1) << MCSR0_RI_SHIFT) 733#define MCSR0_UAL_SHIFT 52 734#define MCSR0_UAL (_ULCAST_(1) << MCSR0_UAL_SHIFT) 735#define MCSR0_VABIT_SHIFT 44 736#define MCSR0_VABIT_WIDTH 8 737#define MCSR0_VABIT (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT) 738#define VABIT_DEFAULT 0x2f 739#define MCSR0_PABIT_SHIFT 36 740#define MCSR0_PABIT_WIDTH 8 741#define MCSR0_PABIT (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT) 742#define PABIT_DEFAULT 0x2f 743#define MCSR0_IOCSR_SHIFT 35 744#define MCSR0_IOCSR (_ULCAST_(1) << MCSR0_IOCSR_SHIFT) 745#define MCSR0_PAGING_SHIFT 34 746#define MCSR0_PAGING (_ULCAST_(1) << MCSR0_PAGING_SHIFT) 747#define MCSR0_GR64_SHIFT 33 748#define MCSR0_GR64 (_ULCAST_(1) << MCSR0_GR64_SHIFT) 749#define GR64_DEFAULT 1 750#define MCSR0_GR32_SHIFT 32 751#define MCSR0_GR32 (_ULCAST_(1) << MCSR0_GR32_SHIFT) 752#define GR32_DEFAULT 0 753#define MCSR0_PRID_WIDTH 32 754#define MCSR0_PRID 0x14C010 755 756#define LOONGARCH_CSR_MCSR1 0xc1 /* CPUCFG2 and CPUCFG3 */ 757#define MCSR1_HPFOLD_SHIFT 43 758#define MCSR1_HPFOLD (_ULCAST_(1) << MCSR1_HPFOLD_SHIFT) 759#define MCSR1_SPW_LVL_SHIFT 40 760#define MCSR1_SPW_LVL_WIDTH 3 761#define MCSR1_SPW_LVL (_ULCAST_(7) << MCSR1_SPW_LVL_SHIFT) 762#define MCSR1_ICACHET_SHIFT 39 763#define MCSR1_ICACHET (_ULCAST_(1) << MCSR1_ICACHET_SHIFT) 764#define MCSR1_ITLBT_SHIFT 38 765#define MCSR1_ITLBT (_ULCAST_(1) << MCSR1_ITLBT_SHIFT) 766#define MCSR1_LLDBAR_SHIFT 37 767#define MCSR1_LLDBAR (_ULCAST_(1) << MCSR1_LLDBAR_SHIFT) 768#define MCSR1_SCDLY_SHIFT 36 769#define MCSR1_SCDLY (_ULCAST_(1) << MCSR1_SCDLY_SHIFT) 770#define MCSR1_LLEXC_SHIFT 35 771#define MCSR1_LLEXC (_ULCAST_(1) << MCSR1_LLEXC_SHIFT) 772#define MCSR1_UCACC_SHIFT 34 773#define MCSR1_UCACC (_ULCAST_(1) << MCSR1_UCACC_SHIFT) 774#define MCSR1_SFB_SHIFT 33 775#define MCSR1_SFB (_ULCAST_(1) << MCSR1_SFB_SHIFT) 776#define MCSR1_CCDMA_SHIFT 32 777#define MCSR1_CCDMA (_ULCAST_(1) << MCSR1_CCDMA_SHIFT) 778#define MCSR1_LAMO_SHIFT 22 779#define MCSR1_LAMO (_ULCAST_(1) << MCSR1_LAMO_SHIFT) 780#define MCSR1_LSPW_SHIFT 21 781#define MCSR1_LSPW (_ULCAST_(1) << MCSR1_LSPW_SHIFT) 782#define MCSR1_MIPSBT_SHIFT 20 783#define MCSR1_MIPSBT (_ULCAST_(1) << MCSR1_MIPSBT_SHIFT) 784#define MCSR1_ARMBT_SHIFT 19 785#define MCSR1_ARMBT (_ULCAST_(1) << MCSR1_ARMBT_SHIFT) 786#define MCSR1_X86BT_SHIFT 18 787#define MCSR1_X86BT (_ULCAST_(1) << MCSR1_X86BT_SHIFT) 788#define MCSR1_LLFTPVERS_SHIFT 15 789#define MCSR1_LLFTPVERS_WIDTH 3 790#define MCSR1_LLFTPVERS (_ULCAST_(7) << MCSR1_LLFTPVERS_SHIFT) 791#define MCSR1_LLFTP_SHIFT 14 792#define MCSR1_LLFTP (_ULCAST_(1) << MCSR1_LLFTP_SHIFT) 793#define MCSR1_VZVERS_SHIFT 11 794#define MCSR1_VZVERS_WIDTH 3 795#define MCSR1_VZVERS (_ULCAST_(7) << MCSR1_VZVERS_SHIFT) 796#define MCSR1_VZ_SHIFT 10 797#define MCSR1_VZ (_ULCAST_(1) << MCSR1_VZ_SHIFT) 798#define MCSR1_CRYPTO_SHIFT 9 799#define MCSR1_CRYPTO (_ULCAST_(1) << MCSR1_CRYPTO_SHIFT) 800#define MCSR1_COMPLEX_SHIFT 8 801#define MCSR1_COMPLEX (_ULCAST_(1) << MCSR1_COMPLEX_SHIFT) 802#define MCSR1_LASX_SHIFT 7 803#define MCSR1_LASX (_ULCAST_(1) << MCSR1_LASX_SHIFT) 804#define MCSR1_LSX_SHIFT 6 805#define MCSR1_LSX (_ULCAST_(1) << MCSR1_LSX_SHIFT) 806#define MCSR1_FPVERS_SHIFT 3 807#define MCSR1_FPVERS_WIDTH 3 808#define MCSR1_FPVERS (_ULCAST_(7) << MCSR1_FPVERS_SHIFT) 809#define MCSR1_FPDP_SHIFT 2 810#define MCSR1_FPDP (_ULCAST_(1) << MCSR1_FPDP_SHIFT) 811#define MCSR1_FPSP_SHIFT 1 812#define MCSR1_FPSP (_ULCAST_(1) << MCSR1_FPSP_SHIFT) 813#define MCSR1_FP_SHIFT 0 814#define MCSR1_FP (_ULCAST_(1) << MCSR1_FP_SHIFT) 815 816#define LOONGARCH_CSR_MCSR2 0xc2 /* CPUCFG4 and CPUCFG5 */ 817#define MCSR2_CCDIV_SHIFT 48 818#define MCSR2_CCDIV_WIDTH 16 819#define MCSR2_CCDIV (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT) 820#define MCSR2_CCMUL_SHIFT 32 821#define MCSR2_CCMUL_WIDTH 16 822#define MCSR2_CCMUL (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT) 823#define MCSR2_CCFREQ_WIDTH 32 824#define MCSR2_CCFREQ (_ULCAST_(0xffffffff)) 825#define CCFREQ_DEFAULT 0x5f5e100 /* 100MHz */ 826 827#define LOONGARCH_CSR_MCSR3 0xc3 /* CPUCFG6 */ 828#define MCSR3_UPM_SHIFT 14 829#define MCSR3_UPM (_ULCAST_(1) << MCSR3_UPM_SHIFT) 830#define MCSR3_PMBITS_SHIFT 8 831#define MCSR3_PMBITS_WIDTH 6 832#define MCSR3_PMBITS (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT) 833#define PMBITS_DEFAULT 0x40 834#define MCSR3_PMNUM_SHIFT 4 835#define MCSR3_PMNUM_WIDTH 4 836#define MCSR3_PMNUM (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT) 837#define MCSR3_PAMVER_SHIFT 1 838#define MCSR3_PAMVER_WIDTH 3 839#define MCSR3_PAMVER (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT) 840#define MCSR3_PMP_SHIFT 0 841#define MCSR3_PMP (_ULCAST_(1) << MCSR3_PMP_SHIFT) 842 843#define LOONGARCH_CSR_MCSR8 0xc8 /* CPUCFG16 and CPUCFG17 */ 844#define MCSR8_L1I_SIZE_SHIFT 56 845#define MCSR8_L1I_SIZE_WIDTH 7 846#define MCSR8_L1I_SIZE (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT) 847#define MCSR8_L1I_IDX_SHIFT 48 848#define MCSR8_L1I_IDX_WIDTH 8 849#define MCSR8_L1I_IDX (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT) 850#define MCSR8_L1I_WAY_SHIFT 32 851#define MCSR8_L1I_WAY_WIDTH 16 852#define MCSR8_L1I_WAY (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT) 853#define MCSR8_L3DINCL_SHIFT 16 854#define MCSR8_L3DINCL (_ULCAST_(1) << MCSR8_L3DINCL_SHIFT) 855#define MCSR8_L3DPRIV_SHIFT 15 856#define MCSR8_L3DPRIV (_ULCAST_(1) << MCSR8_L3DPRIV_SHIFT) 857#define MCSR8_L3DPRE_SHIFT 14 858#define MCSR8_L3DPRE (_ULCAST_(1) << MCSR8_L3DPRE_SHIFT) 859#define MCSR8_L3IUINCL_SHIFT 13 860#define MCSR8_L3IUINCL (_ULCAST_(1) << MCSR8_L3IUINCL_SHIFT) 861#define MCSR8_L3IUPRIV_SHIFT 12 862#define MCSR8_L3IUPRIV (_ULCAST_(1) << MCSR8_L3IUPRIV_SHIFT) 863#define MCSR8_L3IUUNIFY_SHIFT 11 864#define MCSR8_L3IUUNIFY (_ULCAST_(1) << MCSR8_L3IUUNIFY_SHIFT) 865#define MCSR8_L3IUPRE_SHIFT 10 866#define MCSR8_L3IUPRE (_ULCAST_(1) << MCSR8_L3IUPRE_SHIFT) 867#define MCSR8_L2DINCL_SHIFT 9 868#define MCSR8_L2DINCL (_ULCAST_(1) << MCSR8_L2DINCL_SHIFT) 869#define MCSR8_L2DPRIV_SHIFT 8 870#define MCSR8_L2DPRIV (_ULCAST_(1) << MCSR8_L2DPRIV_SHIFT) 871#define MCSR8_L2DPRE_SHIFT 7 872#define MCSR8_L2DPRE (_ULCAST_(1) << MCSR8_L2DPRE_SHIFT) 873#define MCSR8_L2IUINCL_SHIFT 6 874#define MCSR8_L2IUINCL (_ULCAST_(1) << MCSR8_L2IUINCL_SHIFT) 875#define MCSR8_L2IUPRIV_SHIFT 5 876#define MCSR8_L2IUPRIV (_ULCAST_(1) << MCSR8_L2IUPRIV_SHIFT) 877#define MCSR8_L2IUUNIFY_SHIFT 4 878#define MCSR8_L2IUUNIFY (_ULCAST_(1) << MCSR8_L2IUUNIFY_SHIFT) 879#define MCSR8_L2IUPRE_SHIFT 3 880#define MCSR8_L2IUPRE (_ULCAST_(1) << MCSR8_L2IUPRE_SHIFT) 881#define MCSR8_L1DPRE_SHIFT 2 882#define MCSR8_L1DPRE (_ULCAST_(1) << MCSR8_L1DPRE_SHIFT) 883#define MCSR8_L1IUUNIFY_SHIFT 1 884#define MCSR8_L1IUUNIFY (_ULCAST_(1) << MCSR8_L1IUUNIFY_SHIFT) 885#define MCSR8_L1IUPRE_SHIFT 0 886#define MCSR8_L1IUPRE (_ULCAST_(1) << MCSR8_L1IUPRE_SHIFT) 887 888#define LOONGARCH_CSR_MCSR9 0xc9 /* CPUCFG18 and CPUCFG19 */ 889#define MCSR9_L2U_SIZE_SHIFT 56 890#define MCSR9_L2U_SIZE_WIDTH 7 891#define MCSR9_L2U_SIZE (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT) 892#define MCSR9_L2U_IDX_SHIFT 48 893#define MCSR9_L2U_IDX_WIDTH 8 894#define MCSR9_L2U_IDX (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT) 895#define MCSR9_L2U_WAY_SHIFT 32 896#define MCSR9_L2U_WAY_WIDTH 16 897#define MCSR9_L2U_WAY (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT) 898#define MCSR9_L1D_SIZE_SHIFT 24 899#define MCSR9_L1D_SIZE_WIDTH 7 900#define MCSR9_L1D_SIZE (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT) 901#define MCSR9_L1D_IDX_SHIFT 16 902#define MCSR9_L1D_IDX_WIDTH 8 903#define MCSR9_L1D_IDX (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT) 904#define MCSR9_L1D_WAY_SHIFT 0 905#define MCSR9_L1D_WAY_WIDTH 16 906#define MCSR9_L1D_WAY (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT) 907 908#define LOONGARCH_CSR_MCSR10 0xca /* CPUCFG20 */ 909#define MCSR10_L3U_SIZE_SHIFT 24 910#define MCSR10_L3U_SIZE_WIDTH 7 911#define MCSR10_L3U_SIZE (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT) 912#define MCSR10_L3U_IDX_SHIFT 16 913#define MCSR10_L3U_IDX_WIDTH 8 914#define MCSR10_L3U_IDX (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT) 915#define MCSR10_L3U_WAY_SHIFT 0 916#define MCSR10_L3U_WAY_WIDTH 16 917#define MCSR10_L3U_WAY (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT) 918 919#define LOONGARCH_CSR_MCSR24 0xf0 /* cpucfg48 */ 920#define MCSR24_RAMCG_SHIFT 3 921#define MCSR24_RAMCG (_ULCAST_(1) << MCSR24_RAMCG_SHIFT) 922#define MCSR24_VFPUCG_SHIFT 2 923#define MCSR24_VFPUCG (_ULCAST_(1) << MCSR24_VFPUCG_SHIFT) 924#define MCSR24_NAPEN_SHIFT 1 925#define MCSR24_NAPEN (_ULCAST_(1) << MCSR24_NAPEN_SHIFT) 926#define MCSR24_MCSRLOCK_SHIFT 0 927#define MCSR24_MCSRLOCK (_ULCAST_(1) << MCSR24_MCSRLOCK_SHIFT) 928 929/* Uncached accelerate windows registers */ 930#define LOONGARCH_CSR_UCAWIN 0x100 931#define LOONGARCH_CSR_UCAWIN0_LO 0x102 932#define LOONGARCH_CSR_UCAWIN0_HI 0x103 933#define LOONGARCH_CSR_UCAWIN1_LO 0x104 934#define LOONGARCH_CSR_UCAWIN1_HI 0x105 935#define LOONGARCH_CSR_UCAWIN2_LO 0x106 936#define LOONGARCH_CSR_UCAWIN2_HI 0x107 937#define LOONGARCH_CSR_UCAWIN3_LO 0x108 938#define LOONGARCH_CSR_UCAWIN3_HI 0x109 939 940/* Direct Map windows registers */ 941#define LOONGARCH_CSR_DMWIN0 0x180 /* 64 direct map win0: MEM & IF */ 942#define LOONGARCH_CSR_DMWIN1 0x181 /* 64 direct map win1: MEM & IF */ 943#define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */ 944#define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */ 945 946/* Direct Map window 0/1 */ 947#define CSR_DMW0_PLV0 _CONST64_(1 << 0) 948#define CSR_DMW0_VSEG _CONST64_(0x8000) 949#define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) 950#define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0) 951 952#define CSR_DMW1_PLV0 _CONST64_(1 << 0) 953#define CSR_DMW1_MAT _CONST64_(1 << 4) 954#define CSR_DMW1_VSEG _CONST64_(0x9000) 955#define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS) 956#define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0) 957 958/* Performance Counter registers */ 959#define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */ 960#define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */ 961#define LOONGARCH_CSR_PERFCTRL1 0x202 /* 32 perf event 1 config */ 962#define LOONGARCH_CSR_PERFCNTR1 0x203 /* 64 perf event 1 count value */ 963#define LOONGARCH_CSR_PERFCTRL2 0x204 /* 32 perf event 2 config */ 964#define LOONGARCH_CSR_PERFCNTR2 0x205 /* 64 perf event 2 count value */ 965#define LOONGARCH_CSR_PERFCTRL3 0x206 /* 32 perf event 3 config */ 966#define LOONGARCH_CSR_PERFCNTR3 0x207 /* 64 perf event 3 count value */ 967#define CSR_PERFCTRL_PLV0 (_ULCAST_(1) << 16) 968#define CSR_PERFCTRL_PLV1 (_ULCAST_(1) << 17) 969#define CSR_PERFCTRL_PLV2 (_ULCAST_(1) << 18) 970#define CSR_PERFCTRL_PLV3 (_ULCAST_(1) << 19) 971#define CSR_PERFCTRL_IE (_ULCAST_(1) << 20) 972#define CSR_PERFCTRL_GMOD (_ULCAST_(3) << 21) 973#define CSR_PERFCTRL_EVENT 0x3ff 974 975/* Debug registers */ 976#define LOONGARCH_CSR_MWPC 0x300 /* data breakpoint config */ 977#define LOONGARCH_CSR_MWPS 0x301 /* data breakpoint status */ 978 979#define LOONGARCH_CSR_DB0ADDR 0x310 /* data breakpoint 0 address */ 980#define LOONGARCH_CSR_DB0MASK 0x311 /* data breakpoint 0 mask */ 981#define LOONGARCH_CSR_DB0CTL 0x312 /* data breakpoint 0 control */ 982#define LOONGARCH_CSR_DB0ASID 0x313 /* data breakpoint 0 asid */ 983 984#define LOONGARCH_CSR_DB1ADDR 0x318 /* data breakpoint 1 address */ 985#define LOONGARCH_CSR_DB1MASK 0x319 /* data breakpoint 1 mask */ 986#define LOONGARCH_CSR_DB1CTL 0x31a /* data breakpoint 1 control */ 987#define LOONGARCH_CSR_DB1ASID 0x31b /* data breakpoint 1 asid */ 988 989#define LOONGARCH_CSR_DB2ADDR 0x320 /* data breakpoint 2 address */ 990#define LOONGARCH_CSR_DB2MASK 0x321 /* data breakpoint 2 mask */ 991#define LOONGARCH_CSR_DB2CTL 0x322 /* data breakpoint 2 control */ 992#define LOONGARCH_CSR_DB2ASID 0x323 /* data breakpoint 2 asid */ 993 994#define LOONGARCH_CSR_DB3ADDR 0x328 /* data breakpoint 3 address */ 995#define LOONGARCH_CSR_DB3MASK 0x329 /* data breakpoint 3 mask */ 996#define LOONGARCH_CSR_DB3CTL 0x32a /* data breakpoint 3 control */ 997#define LOONGARCH_CSR_DB3ASID 0x32b /* data breakpoint 3 asid */ 998 999#define LOONGARCH_CSR_DB4ADDR 0x330 /* data breakpoint 4 address */ 1000#define LOONGARCH_CSR_DB4MASK 0x331 /* data breakpoint 4 maks */ 1001#define LOONGARCH_CSR_DB4CTL 0x332 /* data breakpoint 4 control */ 1002#define LOONGARCH_CSR_DB4ASID 0x333 /* data breakpoint 4 asid */ 1003 1004#define LOONGARCH_CSR_DB5ADDR 0x338 /* data breakpoint 5 address */ 1005#define LOONGARCH_CSR_DB5MASK 0x339 /* data breakpoint 5 mask */ 1006#define LOONGARCH_CSR_DB5CTL 0x33a /* data breakpoint 5 control */ 1007#define LOONGARCH_CSR_DB5ASID 0x33b /* data breakpoint 5 asid */ 1008 1009#define LOONGARCH_CSR_DB6ADDR 0x340 /* data breakpoint 6 address */ 1010#define LOONGARCH_CSR_DB6MASK 0x341 /* data breakpoint 6 mask */ 1011#define LOONGARCH_CSR_DB6CTL 0x342 /* data breakpoint 6 control */ 1012#define LOONGARCH_CSR_DB6ASID 0x343 /* data breakpoint 6 asid */ 1013 1014#define LOONGARCH_CSR_DB7ADDR 0x348 /* data breakpoint 7 address */ 1015#define LOONGARCH_CSR_DB7MASK 0x349 /* data breakpoint 7 mask */ 1016#define LOONGARCH_CSR_DB7CTL 0x34a /* data breakpoint 7 control */ 1017#define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */ 1018 1019#define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */ 1020#define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */ 1021 1022#define LOONGARCH_CSR_IB0ADDR 0x390 /* inst breakpoint 0 address */ 1023#define LOONGARCH_CSR_IB0MASK 0x391 /* inst breakpoint 0 mask */ 1024#define LOONGARCH_CSR_IB0CTL 0x392 /* inst breakpoint 0 control */ 1025#define LOONGARCH_CSR_IB0ASID 0x393 /* inst breakpoint 0 asid */ 1026 1027#define LOONGARCH_CSR_IB1ADDR 0x398 /* inst breakpoint 1 address */ 1028#define LOONGARCH_CSR_IB1MASK 0x399 /* inst breakpoint 1 mask */ 1029#define LOONGARCH_CSR_IB1CTL 0x39a /* inst breakpoint 1 control */ 1030#define LOONGARCH_CSR_IB1ASID 0x39b /* inst breakpoint 1 asid */ 1031 1032#define LOONGARCH_CSR_IB2ADDR 0x3a0 /* inst breakpoint 2 address */ 1033#define LOONGARCH_CSR_IB2MASK 0x3a1 /* inst breakpoint 2 mask */ 1034#define LOONGARCH_CSR_IB2CTL 0x3a2 /* inst breakpoint 2 control */ 1035#define LOONGARCH_CSR_IB2ASID 0x3a3 /* inst breakpoint 2 asid */ 1036 1037#define LOONGARCH_CSR_IB3ADDR 0x3a8 /* inst breakpoint 3 address */ 1038#define LOONGARCH_CSR_IB3MASK 0x3a9 /* breakpoint 3 mask */ 1039#define LOONGARCH_CSR_IB3CTL 0x3aa /* inst breakpoint 3 control */ 1040#define LOONGARCH_CSR_IB3ASID 0x3ab /* inst breakpoint 3 asid */ 1041 1042#define LOONGARCH_CSR_IB4ADDR 0x3b0 /* inst breakpoint 4 address */ 1043#define LOONGARCH_CSR_IB4MASK 0x3b1 /* inst breakpoint 4 mask */ 1044#define LOONGARCH_CSR_IB4CTL 0x3b2 /* inst breakpoint 4 control */ 1045#define LOONGARCH_CSR_IB4ASID 0x3b3 /* inst breakpoint 4 asid */ 1046 1047#define LOONGARCH_CSR_IB5ADDR 0x3b8 /* inst breakpoint 5 address */ 1048#define LOONGARCH_CSR_IB5MASK 0x3b9 /* inst breakpoint 5 mask */ 1049#define LOONGARCH_CSR_IB5CTL 0x3ba /* inst breakpoint 5 control */ 1050#define LOONGARCH_CSR_IB5ASID 0x3bb /* inst breakpoint 5 asid */ 1051 1052#define LOONGARCH_CSR_IB6ADDR 0x3c0 /* inst breakpoint 6 address */ 1053#define LOONGARCH_CSR_IB6MASK 0x3c1 /* inst breakpoint 6 mask */ 1054#define LOONGARCH_CSR_IB6CTL 0x3c2 /* inst breakpoint 6 control */ 1055#define LOONGARCH_CSR_IB6ASID 0x3c3 /* inst breakpoint 6 asid */ 1056 1057#define LOONGARCH_CSR_IB7ADDR 0x3c8 /* inst breakpoint 7 address */ 1058#define LOONGARCH_CSR_IB7MASK 0x3c9 /* inst breakpoint 7 mask */ 1059#define LOONGARCH_CSR_IB7CTL 0x3ca /* inst breakpoint 7 control */ 1060#define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */ 1061 1062#define LOONGARCH_CSR_DEBUG 0x500 /* debug config */ 1063#define LOONGARCH_CSR_DERA 0x501 /* debug era */ 1064#define LOONGARCH_CSR_DESAVE 0x502 /* debug save */ 1065 1066/* 1067 * CSR_ECFG IM 1068 */ 1069#define ECFG0_IM 0x00001fff 1070#define ECFGB_SIP0 0 1071#define ECFGF_SIP0 (_ULCAST_(1) << ECFGB_SIP0) 1072#define ECFGB_SIP1 1 1073#define ECFGF_SIP1 (_ULCAST_(1) << ECFGB_SIP1) 1074#define ECFGB_IP0 2 1075#define ECFGF_IP0 (_ULCAST_(1) << ECFGB_IP0) 1076#define ECFGB_IP1 3 1077#define ECFGF_IP1 (_ULCAST_(1) << ECFGB_IP1) 1078#define ECFGB_IP2 4 1079#define ECFGF_IP2 (_ULCAST_(1) << ECFGB_IP2) 1080#define ECFGB_IP3 5 1081#define ECFGF_IP3 (_ULCAST_(1) << ECFGB_IP3) 1082#define ECFGB_IP4 6 1083#define ECFGF_IP4 (_ULCAST_(1) << ECFGB_IP4) 1084#define ECFGB_IP5 7 1085#define ECFGF_IP5 (_ULCAST_(1) << ECFGB_IP5) 1086#define ECFGB_IP6 8 1087#define ECFGF_IP6 (_ULCAST_(1) << ECFGB_IP6) 1088#define ECFGB_IP7 9 1089#define ECFGF_IP7 (_ULCAST_(1) << ECFGB_IP7) 1090#define ECFGB_PMC 10 1091#define ECFGF_PMC (_ULCAST_(1) << ECFGB_PMC) 1092#define ECFGB_TIMER 11 1093#define ECFGF_TIMER (_ULCAST_(1) << ECFGB_TIMER) 1094#define ECFGB_IPI 12 1095#define ECFGF_IPI (_ULCAST_(1) << ECFGB_IPI) 1096#define ECFGF(hwirq) (_ULCAST_(1) << hwirq) 1097 1098#define ESTATF_IP 0x00003fff 1099 1100#define LOONGARCH_IOCSR_FEATURES 0x8 1101#define IOCSRF_TEMP BIT_ULL(0) 1102#define IOCSRF_NODECNT BIT_ULL(1) 1103#define IOCSRF_MSI BIT_ULL(2) 1104#define IOCSRF_EXTIOI BIT_ULL(3) 1105#define IOCSRF_CSRIPI BIT_ULL(4) 1106#define IOCSRF_FREQCSR BIT_ULL(5) 1107#define IOCSRF_FREQSCALE BIT_ULL(6) 1108#define IOCSRF_DVFSV1 BIT_ULL(7) 1109#define IOCSRF_EIODECODE BIT_ULL(9) 1110#define IOCSRF_FLATMODE BIT_ULL(10) 1111#define IOCSRF_VM BIT_ULL(11) 1112 1113#define LOONGARCH_IOCSR_VENDOR 0x10 1114 1115#define LOONGARCH_IOCSR_CPUNAME 0x20 1116 1117#define LOONGARCH_IOCSR_NODECNT 0x408 1118 1119#define LOONGARCH_IOCSR_MISC_FUNC 0x420 1120#define IOCSR_MISC_FUNC_SOFT_INT BIT_ULL(10) 1121#define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21) 1122#define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48) 1123 1124#define LOONGARCH_IOCSR_CPUTEMP 0x428 1125 1126#define LOONGARCH_IOCSR_SMCMBX 0x51c 1127 1128/* PerCore CSR, only accessable by local cores */ 1129#define LOONGARCH_IOCSR_IPI_STATUS 0x1000 1130#define LOONGARCH_IOCSR_IPI_EN 0x1004 1131#define LOONGARCH_IOCSR_IPI_SET 0x1008 1132#define LOONGARCH_IOCSR_IPI_CLEAR 0x100c 1133#define LOONGARCH_IOCSR_MBUF0 0x1020 1134#define LOONGARCH_IOCSR_MBUF1 0x1028 1135#define LOONGARCH_IOCSR_MBUF2 0x1030 1136#define LOONGARCH_IOCSR_MBUF3 0x1038 1137 1138#define LOONGARCH_IOCSR_IPI_SEND 0x1040 1139#define IOCSR_IPI_SEND_IP_SHIFT 0 1140#define IOCSR_IPI_SEND_CPU_SHIFT 16 1141#define IOCSR_IPI_SEND_BLOCKING BIT(31) 1142 1143#define LOONGARCH_IOCSR_MBUF_SEND 0x1048 1144#define IOCSR_MBUF_SEND_BLOCKING BIT_ULL(31) 1145#define IOCSR_MBUF_SEND_BOX_SHIFT 2 1146#define IOCSR_MBUF_SEND_BOX_LO(box) (box << 1) 1147#define IOCSR_MBUF_SEND_BOX_HI(box) ((box << 1) + 1) 1148#define IOCSR_MBUF_SEND_CPU_SHIFT 16 1149#define IOCSR_MBUF_SEND_BUF_SHIFT 32 1150#define IOCSR_MBUF_SEND_H32_MASK 0xFFFFFFFF00000000ULL 1151 1152#define LOONGARCH_IOCSR_ANY_SEND 0x1158 1153#define IOCSR_ANY_SEND_BLOCKING BIT_ULL(31) 1154#define IOCSR_ANY_SEND_CPU_SHIFT 16 1155#define IOCSR_ANY_SEND_MASK_SHIFT 27 1156#define IOCSR_ANY_SEND_BUF_SHIFT 32 1157#define IOCSR_ANY_SEND_H32_MASK 0xFFFFFFFF00000000ULL 1158 1159/* Register offset and bit definition for CSR access */ 1160#define LOONGARCH_IOCSR_TIMER_CFG 0x1060 1161#define LOONGARCH_IOCSR_TIMER_TICK 0x1070 1162#define IOCSR_TIMER_CFG_RESERVED (_ULCAST_(1) << 63) 1163#define IOCSR_TIMER_CFG_PERIODIC (_ULCAST_(1) << 62) 1164#define IOCSR_TIMER_CFG_EN (_ULCAST_(1) << 61) 1165#define IOCSR_TIMER_MASK 0x0ffffffffffffULL 1166#define IOCSR_TIMER_INITVAL_RST (_ULCAST_(0xffff) << 48) 1167 1168#define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE 0x14a0 1169#define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE 0x14c0 1170#define LOONGARCH_IOCSR_EXTIOI_EN_BASE 0x1600 1171#define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE 0x1680 1172#define LOONGARCH_IOCSR_EXTIOI_ISR_BASE 0x1800 1173#define LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE 0x1c00 1174#define IOCSR_EXTIOI_VECTOR_NUM 256 1175 1176#ifndef __ASSEMBLY__ 1177 1178static inline u64 drdtime(void) 1179{ 1180 u64 val = 0; 1181 1182 __asm__ __volatile__( 1183 "rdtime.d %0, $zero\n\t" 1184 : "=r"(val) 1185 : 1186 ); 1187 return val; 1188} 1189 1190static inline unsigned int get_csr_cpuid(void) 1191{ 1192 return csr_read32(LOONGARCH_CSR_CPUID); 1193} 1194 1195static inline void csr_any_send(unsigned int addr, unsigned int data, 1196 unsigned int data_mask, unsigned int cpu) 1197{ 1198 uint64_t val = 0; 1199 1200 val = IOCSR_ANY_SEND_BLOCKING | addr; 1201 val |= (cpu << IOCSR_ANY_SEND_CPU_SHIFT); 1202 val |= (data_mask << IOCSR_ANY_SEND_MASK_SHIFT); 1203 val |= ((uint64_t)data << IOCSR_ANY_SEND_BUF_SHIFT); 1204 iocsr_write64(val, LOONGARCH_IOCSR_ANY_SEND); 1205} 1206 1207static inline unsigned int read_csr_excode(void) 1208{ 1209 return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; 1210} 1211 1212static inline void write_csr_index(unsigned int idx) 1213{ 1214 csr_xchg32(idx, CSR_TLBIDX_IDXM, LOONGARCH_CSR_TLBIDX); 1215} 1216 1217static inline unsigned int read_csr_pagesize(void) 1218{ 1219 return (csr_read32(LOONGARCH_CSR_TLBIDX) & CSR_TLBIDX_SIZEM) >> CSR_TLBIDX_SIZE; 1220} 1221 1222static inline void write_csr_pagesize(unsigned int size) 1223{ 1224 csr_xchg32(size << CSR_TLBIDX_SIZE, CSR_TLBIDX_SIZEM, LOONGARCH_CSR_TLBIDX); 1225} 1226 1227static inline unsigned int read_csr_tlbrefill_pagesize(void) 1228{ 1229 return (csr_read64(LOONGARCH_CSR_TLBREHI) & CSR_TLBREHI_PS) >> CSR_TLBREHI_PS_SHIFT; 1230} 1231 1232static inline void write_csr_tlbrefill_pagesize(unsigned int size) 1233{ 1234 csr_xchg64(size << CSR_TLBREHI_PS_SHIFT, CSR_TLBREHI_PS, LOONGARCH_CSR_TLBREHI); 1235} 1236 1237#define read_csr_asid() csr_read32(LOONGARCH_CSR_ASID) 1238#define write_csr_asid(val) csr_write32(val, LOONGARCH_CSR_ASID) 1239#define read_csr_entryhi() csr_read64(LOONGARCH_CSR_TLBEHI) 1240#define write_csr_entryhi(val) csr_write64(val, LOONGARCH_CSR_TLBEHI) 1241#define read_csr_entrylo0() csr_read64(LOONGARCH_CSR_TLBELO0) 1242#define write_csr_entrylo0(val) csr_write64(val, LOONGARCH_CSR_TLBELO0) 1243#define read_csr_entrylo1() csr_read64(LOONGARCH_CSR_TLBELO1) 1244#define write_csr_entrylo1(val) csr_write64(val, LOONGARCH_CSR_TLBELO1) 1245#define read_csr_ecfg() csr_read32(LOONGARCH_CSR_ECFG) 1246#define write_csr_ecfg(val) csr_write32(val, LOONGARCH_CSR_ECFG) 1247#define read_csr_estat() csr_read32(LOONGARCH_CSR_ESTAT) 1248#define write_csr_estat(val) csr_write32(val, LOONGARCH_CSR_ESTAT) 1249#define read_csr_tlbidx() csr_read32(LOONGARCH_CSR_TLBIDX) 1250#define write_csr_tlbidx(val) csr_write32(val, LOONGARCH_CSR_TLBIDX) 1251#define read_csr_euen() csr_read32(LOONGARCH_CSR_EUEN) 1252#define write_csr_euen(val) csr_write32(val, LOONGARCH_CSR_EUEN) 1253#define read_csr_cpuid() csr_read32(LOONGARCH_CSR_CPUID) 1254#define read_csr_prcfg1() csr_read64(LOONGARCH_CSR_PRCFG1) 1255#define write_csr_prcfg1(val) csr_write64(val, LOONGARCH_CSR_PRCFG1) 1256#define read_csr_prcfg2() csr_read64(LOONGARCH_CSR_PRCFG2) 1257#define write_csr_prcfg2(val) csr_write64(val, LOONGARCH_CSR_PRCFG2) 1258#define read_csr_prcfg3() csr_read64(LOONGARCH_CSR_PRCFG3) 1259#define write_csr_prcfg3(val) csr_write64(val, LOONGARCH_CSR_PRCFG3) 1260#define read_csr_stlbpgsize() csr_read32(LOONGARCH_CSR_STLBPGSIZE) 1261#define write_csr_stlbpgsize(val) csr_write32(val, LOONGARCH_CSR_STLBPGSIZE) 1262#define read_csr_rvacfg() csr_read32(LOONGARCH_CSR_RVACFG) 1263#define write_csr_rvacfg(val) csr_write32(val, LOONGARCH_CSR_RVACFG) 1264#define write_csr_tintclear(val) csr_write32(val, LOONGARCH_CSR_TINTCLR) 1265#define read_csr_impctl1() csr_read64(LOONGARCH_CSR_IMPCTL1) 1266#define write_csr_impctl1(val) csr_write64(val, LOONGARCH_CSR_IMPCTL1) 1267#define write_csr_impctl2(val) csr_write64(val, LOONGARCH_CSR_IMPCTL2) 1268 1269#define read_csr_perfctrl0() csr_read64(LOONGARCH_CSR_PERFCTRL0) 1270#define read_csr_perfcntr0() csr_read64(LOONGARCH_CSR_PERFCNTR0) 1271#define read_csr_perfctrl1() csr_read64(LOONGARCH_CSR_PERFCTRL1) 1272#define read_csr_perfcntr1() csr_read64(LOONGARCH_CSR_PERFCNTR1) 1273#define read_csr_perfctrl2() csr_read64(LOONGARCH_CSR_PERFCTRL2) 1274#define read_csr_perfcntr2() csr_read64(LOONGARCH_CSR_PERFCNTR2) 1275#define read_csr_perfctrl3() csr_read64(LOONGARCH_CSR_PERFCTRL3) 1276#define read_csr_perfcntr3() csr_read64(LOONGARCH_CSR_PERFCNTR3) 1277#define write_csr_perfctrl0(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL0) 1278#define write_csr_perfcntr0(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR0) 1279#define write_csr_perfctrl1(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL1) 1280#define write_csr_perfcntr1(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR1) 1281#define write_csr_perfctrl2(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL2) 1282#define write_csr_perfcntr2(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR2) 1283#define write_csr_perfctrl3(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL3) 1284#define write_csr_perfcntr3(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR3) 1285 1286/* Guest related CSRS */ 1287#define read_csr_gtlbc() csr_read32(LOONGARCH_CSR_GTLBC) 1288#define write_csr_gtlbc(val) csr_write32(val, LOONGARCH_CSR_GTLBC) 1289#define read_csr_trgp() csr_read32(LOONGARCH_CSR_TRGP) 1290#define read_csr_gcfg() csr_read32(LOONGARCH_CSR_GCFG) 1291#define write_csr_gcfg(val) csr_write32(val, LOONGARCH_CSR_GCFG) 1292#define read_csr_gstat() csr_read32(LOONGARCH_CSR_GSTAT) 1293#define write_csr_gstat(val) csr_write32(val, LOONGARCH_CSR_GSTAT) 1294#define read_csr_gintc() csr_read32(LOONGARCH_CSR_GINTC) 1295#define write_csr_gintc(val) csr_write32(val, LOONGARCH_CSR_GINTC) 1296#define read_csr_gcntc() csr_read64(LOONGARCH_CSR_GCNTC) 1297#define write_csr_gcntc(val) csr_write64(val, LOONGARCH_CSR_GCNTC) 1298 1299/* Guest CSRS read and write */ 1300#define read_gcsr_crmd() gcsr_read(LOONGARCH_CSR_CRMD) 1301#define write_gcsr_crmd(val) gcsr_write(val, LOONGARCH_CSR_CRMD) 1302#define read_gcsr_prmd() gcsr_read(LOONGARCH_CSR_PRMD) 1303#define write_gcsr_prmd(val) gcsr_write(val, LOONGARCH_CSR_PRMD) 1304#define read_gcsr_euen() gcsr_read(LOONGARCH_CSR_EUEN) 1305#define write_gcsr_euen(val) gcsr_write(val, LOONGARCH_CSR_EUEN) 1306#define read_gcsr_misc() gcsr_read(LOONGARCH_CSR_MISC) 1307#define write_gcsr_misc(val) gcsr_write(val, LOONGARCH_CSR_MISC) 1308#define read_gcsr_ecfg() gcsr_read(LOONGARCH_CSR_ECFG) 1309#define write_gcsr_ecfg(val) gcsr_write(val, LOONGARCH_CSR_ECFG) 1310#define read_gcsr_estat() gcsr_read(LOONGARCH_CSR_ESTAT) 1311#define write_gcsr_estat(val) gcsr_write(val, LOONGARCH_CSR_ESTAT) 1312#define read_gcsr_era() gcsr_read(LOONGARCH_CSR_ERA) 1313#define write_gcsr_era(val) gcsr_write(val, LOONGARCH_CSR_ERA) 1314#define read_gcsr_badv() gcsr_read(LOONGARCH_CSR_BADV) 1315#define write_gcsr_badv(val) gcsr_write(val, LOONGARCH_CSR_BADV) 1316#define read_gcsr_badi() gcsr_read(LOONGARCH_CSR_BADI) 1317#define write_gcsr_badi(val) gcsr_write(val, LOONGARCH_CSR_BADI) 1318#define read_gcsr_eentry() gcsr_read(LOONGARCH_CSR_EENTRY) 1319#define write_gcsr_eentry(val) gcsr_write(val, LOONGARCH_CSR_EENTRY) 1320 1321#define read_gcsr_tlbidx() gcsr_read(LOONGARCH_CSR_TLBIDX) 1322#define write_gcsr_tlbidx(val) gcsr_write(val, LOONGARCH_CSR_TLBIDX) 1323#define read_gcsr_tlbhi() gcsr_read(LOONGARCH_CSR_TLBEHI) 1324#define write_gcsr_tlbhi(val) gcsr_write(val, LOONGARCH_CSR_TLBEHI) 1325#define read_gcsr_tlblo0() gcsr_read(LOONGARCH_CSR_TLBELO0) 1326#define write_gcsr_tlblo0(val) gcsr_write(val, LOONGARCH_CSR_TLBELO0) 1327#define read_gcsr_tlblo1() gcsr_read(LOONGARCH_CSR_TLBELO1) 1328#define write_gcsr_tlblo1(val) gcsr_write(val, LOONGARCH_CSR_TLBELO1) 1329 1330#define read_gcsr_asid() gcsr_read(LOONGARCH_CSR_ASID) 1331#define write_gcsr_asid(val) gcsr_write(val, LOONGARCH_CSR_ASID) 1332#define read_gcsr_pgdl() gcsr_read(LOONGARCH_CSR_PGDL) 1333#define write_gcsr_pgdl(val) gcsr_write(val, LOONGARCH_CSR_PGDL) 1334#define read_gcsr_pgdh() gcsr_read(LOONGARCH_CSR_PGDH) 1335#define write_gcsr_pgdh(val) gcsr_write(val, LOONGARCH_CSR_PGDH) 1336#define read_gcsr_pgd() gcsr_read(LOONGARCH_CSR_PGD) 1337#define write_gcsr_pgd(val) gcsr_write(val, LOONGARCH_CSR_PGD) 1338#define read_gcsr_pwctl0() gcsr_read(LOONGARCH_CSR_PWCTL0) 1339#define write_gcsr_pwctl0(val) gcsr_write(val, LOONGARCH_CSR_PWCTL0) 1340#define read_gcsr_pwctl1() gcsr_read(LOONGARCH_CSR_PWCTL1) 1341#define write_gcsr_pwctl1(val) gcsr_write(val, LOONGARCH_CSR_PWCTL1) 1342#define read_gcsr_stlbpgsize() gcsr_read(LOONGARCH_CSR_STLBPGSIZE) 1343#define write_gcsr_stlbpgsize(val) gcsr_write(val, LOONGARCH_CSR_STLBPGSIZE) 1344#define read_gcsr_rvacfg() gcsr_read(LOONGARCH_CSR_RVACFG) 1345#define write_gcsr_rvacfg(val) gcsr_write(val, LOONGARCH_CSR_RVACFG) 1346 1347#define read_gcsr_cpuid() gcsr_read(LOONGARCH_CSR_CPUID) 1348#define write_gcsr_cpuid(val) gcsr_write(val, LOONGARCH_CSR_CPUID) 1349#define read_gcsr_prcfg1() gcsr_read(LOONGARCH_CSR_PRCFG1) 1350#define write_gcsr_prcfg1(val) gcsr_write(val, LOONGARCH_CSR_PRCFG1) 1351#define read_gcsr_prcfg2() gcsr_read(LOONGARCH_CSR_PRCFG2) 1352#define write_gcsr_prcfg2(val) gcsr_write(val, LOONGARCH_CSR_PRCFG2) 1353#define read_gcsr_prcfg3() gcsr_read(LOONGARCH_CSR_PRCFG3) 1354#define write_gcsr_prcfg3(val) gcsr_write(val, LOONGARCH_CSR_PRCFG3) 1355 1356#define read_gcsr_kscratch0() gcsr_read(LOONGARCH_CSR_KS0) 1357#define write_gcsr_kscratch0(val) gcsr_write(val, LOONGARCH_CSR_KS0) 1358#define read_gcsr_kscratch1() gcsr_read(LOONGARCH_CSR_KS1) 1359#define write_gcsr_kscratch1(val) gcsr_write(val, LOONGARCH_CSR_KS1) 1360#define read_gcsr_kscratch2() gcsr_read(LOONGARCH_CSR_KS2) 1361#define write_gcsr_kscratch2(val) gcsr_write(val, LOONGARCH_CSR_KS2) 1362#define read_gcsr_kscratch3() gcsr_read(LOONGARCH_CSR_KS3) 1363#define write_gcsr_kscratch3(val) gcsr_write(val, LOONGARCH_CSR_KS3) 1364#define read_gcsr_kscratch4() gcsr_read(LOONGARCH_CSR_KS4) 1365#define write_gcsr_kscratch4(val) gcsr_write(val, LOONGARCH_CSR_KS4) 1366#define read_gcsr_kscratch5() gcsr_read(LOONGARCH_CSR_KS5) 1367#define write_gcsr_kscratch5(val) gcsr_write(val, LOONGARCH_CSR_KS5) 1368#define read_gcsr_kscratch6() gcsr_read(LOONGARCH_CSR_KS6) 1369#define write_gcsr_kscratch6(val) gcsr_write(val, LOONGARCH_CSR_KS6) 1370#define read_gcsr_kscratch7() gcsr_read(LOONGARCH_CSR_KS7) 1371#define write_gcsr_kscratch7(val) gcsr_write(val, LOONGARCH_CSR_KS7) 1372 1373#define read_gcsr_timerid() gcsr_read(LOONGARCH_CSR_TMID) 1374#define write_gcsr_timerid(val) gcsr_write(val, LOONGARCH_CSR_TMID) 1375#define read_gcsr_timercfg() gcsr_read(LOONGARCH_CSR_TCFG) 1376#define write_gcsr_timercfg(val) gcsr_write(val, LOONGARCH_CSR_TCFG) 1377#define read_gcsr_timertick() gcsr_read(LOONGARCH_CSR_TVAL) 1378#define write_gcsr_timertick(val) gcsr_write(val, LOONGARCH_CSR_TVAL) 1379#define read_gcsr_timeroffset() gcsr_read(LOONGARCH_CSR_CNTC) 1380#define write_gcsr_timeroffset(val) gcsr_write(val, LOONGARCH_CSR_CNTC) 1381 1382#define read_gcsr_llbctl() gcsr_read(LOONGARCH_CSR_LLBCTL) 1383#define write_gcsr_llbctl(val) gcsr_write(val, LOONGARCH_CSR_LLBCTL) 1384 1385#define read_gcsr_tlbrentry() gcsr_read(LOONGARCH_CSR_TLBRENTRY) 1386#define write_gcsr_tlbrentry(val) gcsr_write(val, LOONGARCH_CSR_TLBRENTRY) 1387#define read_gcsr_tlbrbadv() gcsr_read(LOONGARCH_CSR_TLBRBADV) 1388#define write_gcsr_tlbrbadv(val) gcsr_write(val, LOONGARCH_CSR_TLBRBADV) 1389#define read_gcsr_tlbrera() gcsr_read(LOONGARCH_CSR_TLBRERA) 1390#define write_gcsr_tlbrera(val) gcsr_write(val, LOONGARCH_CSR_TLBRERA) 1391#define read_gcsr_tlbrsave() gcsr_read(LOONGARCH_CSR_TLBRSAVE) 1392#define write_gcsr_tlbrsave(val) gcsr_write(val, LOONGARCH_CSR_TLBRSAVE) 1393#define read_gcsr_tlbrelo0() gcsr_read(LOONGARCH_CSR_TLBRELO0) 1394#define write_gcsr_tlbrelo0(val) gcsr_write(val, LOONGARCH_CSR_TLBRELO0) 1395#define read_gcsr_tlbrelo1() gcsr_read(LOONGARCH_CSR_TLBRELO1) 1396#define write_gcsr_tlbrelo1(val) gcsr_write(val, LOONGARCH_CSR_TLBRELO1) 1397#define read_gcsr_tlbrehi() gcsr_read(LOONGARCH_CSR_TLBREHI) 1398#define write_gcsr_tlbrehi(val) gcsr_write(val, LOONGARCH_CSR_TLBREHI) 1399#define read_gcsr_tlbrprmd() gcsr_read(LOONGARCH_CSR_TLBRPRMD) 1400#define write_gcsr_tlbrprmd(val) gcsr_write(val, LOONGARCH_CSR_TLBRPRMD) 1401 1402#define read_gcsr_directwin0() gcsr_read(LOONGARCH_CSR_DMWIN0) 1403#define write_gcsr_directwin0(val) gcsr_write(val, LOONGARCH_CSR_DMWIN0) 1404#define read_gcsr_directwin1() gcsr_read(LOONGARCH_CSR_DMWIN1) 1405#define write_gcsr_directwin1(val) gcsr_write(val, LOONGARCH_CSR_DMWIN1) 1406#define read_gcsr_directwin2() gcsr_read(LOONGARCH_CSR_DMWIN2) 1407#define write_gcsr_directwin2(val) gcsr_write(val, LOONGARCH_CSR_DMWIN2) 1408#define read_gcsr_directwin3() gcsr_read(LOONGARCH_CSR_DMWIN3) 1409#define write_gcsr_directwin3(val) gcsr_write(val, LOONGARCH_CSR_DMWIN3) 1410 1411/* 1412 * Manipulate bits in a register. 1413 */ 1414#define __BUILD_CSR_COMMON(name) \ 1415static inline unsigned long \ 1416set_##name(unsigned long set) \ 1417{ \ 1418 unsigned long res, new; \ 1419 \ 1420 res = read_##name(); \ 1421 new = res | set; \ 1422 write_##name(new); \ 1423 \ 1424 return res; \ 1425} \ 1426 \ 1427static inline unsigned long \ 1428clear_##name(unsigned long clear) \ 1429{ \ 1430 unsigned long res, new; \ 1431 \ 1432 res = read_##name(); \ 1433 new = res & ~clear; \ 1434 write_##name(new); \ 1435 \ 1436 return res; \ 1437} \ 1438 \ 1439static inline unsigned long \ 1440change_##name(unsigned long change, unsigned long val) \ 1441{ \ 1442 unsigned long res, new; \ 1443 \ 1444 res = read_##name(); \ 1445 new = res & ~change; \ 1446 new |= (val & change); \ 1447 write_##name(new); \ 1448 \ 1449 return res; \ 1450} 1451 1452#define __BUILD_CSR_OP(name) __BUILD_CSR_COMMON(csr_##name) 1453#define __BUILD_GCSR_OP(name) __BUILD_CSR_COMMON(gcsr_##name) 1454 1455__BUILD_CSR_OP(euen) 1456__BUILD_CSR_OP(ecfg) 1457__BUILD_CSR_OP(tlbidx) 1458__BUILD_CSR_OP(gcfg) 1459__BUILD_CSR_OP(gstat) 1460__BUILD_CSR_OP(gtlbc) 1461__BUILD_CSR_OP(gintc) 1462__BUILD_GCSR_OP(llbctl) 1463__BUILD_GCSR_OP(tlbidx) 1464 1465#define set_csr_estat(val) \ 1466 csr_xchg32(val, val, LOONGARCH_CSR_ESTAT) 1467#define clear_csr_estat(val) \ 1468 csr_xchg32(~(val), val, LOONGARCH_CSR_ESTAT) 1469#define set_gcsr_estat(val) \ 1470 gcsr_xchg(val, val, LOONGARCH_CSR_ESTAT) 1471#define clear_gcsr_estat(val) \ 1472 gcsr_xchg(~(val), val, LOONGARCH_CSR_ESTAT) 1473 1474#endif /* __ASSEMBLY__ */ 1475 1476/* Generic EntryLo bit definitions */ 1477#define ENTRYLO_V (_ULCAST_(1) << 0) 1478#define ENTRYLO_D (_ULCAST_(1) << 1) 1479#define ENTRYLO_PLV_SHIFT 2 1480#define ENTRYLO_PLV (_ULCAST_(3) << ENTRYLO_PLV_SHIFT) 1481#define ENTRYLO_C_SHIFT 4 1482#define ENTRYLO_C (_ULCAST_(3) << ENTRYLO_C_SHIFT) 1483#define ENTRYLO_G (_ULCAST_(1) << 6) 1484#define ENTRYLO_NR (_ULCAST_(1) << 61) 1485#define ENTRYLO_NX (_ULCAST_(1) << 62) 1486 1487/* Values for PageMask register */ 1488#define PS_4K 0x0000000c 1489#define PS_8K 0x0000000d 1490#define PS_16K 0x0000000e 1491#define PS_32K 0x0000000f 1492#define PS_64K 0x00000010 1493#define PS_128K 0x00000011 1494#define PS_256K 0x00000012 1495#define PS_512K 0x00000013 1496#define PS_1M 0x00000014 1497#define PS_2M 0x00000015 1498#define PS_4M 0x00000016 1499#define PS_8M 0x00000017 1500#define PS_16M 0x00000018 1501#define PS_32M 0x00000019 1502#define PS_64M 0x0000001a 1503#define PS_128M 0x0000001b 1504#define PS_256M 0x0000001c 1505#define PS_512M 0x0000001d 1506#define PS_1G 0x0000001e 1507 1508/* Default page size for a given kernel configuration */ 1509#ifdef CONFIG_PAGE_SIZE_4KB 1510#define PS_DEFAULT_SIZE PS_4K 1511#elif defined(CONFIG_PAGE_SIZE_16KB) 1512#define PS_DEFAULT_SIZE PS_16K 1513#elif defined(CONFIG_PAGE_SIZE_64KB) 1514#define PS_DEFAULT_SIZE PS_64K 1515#else 1516#error Bad page size configuration! 1517#endif 1518 1519/* Default huge tlb size for a given kernel configuration */ 1520#ifdef CONFIG_PAGE_SIZE_4KB 1521#define PS_HUGE_SIZE PS_1M 1522#elif defined(CONFIG_PAGE_SIZE_16KB) 1523#define PS_HUGE_SIZE PS_16M 1524#elif defined(CONFIG_PAGE_SIZE_64KB) 1525#define PS_HUGE_SIZE PS_256M 1526#else 1527#error Bad page size configuration for hugetlbfs! 1528#endif 1529 1530/* ExStatus.ExcCode */ 1531#define EXCCODE_RSV 0 /* Reserved */ 1532#define EXCCODE_TLBL 1 /* TLB miss on a load */ 1533#define EXCCODE_TLBS 2 /* TLB miss on a store */ 1534#define EXCCODE_TLBI 3 /* TLB miss on a ifetch */ 1535#define EXCCODE_TLBM 4 /* TLB modified fault */ 1536#define EXCCODE_TLBNR 5 /* TLB Read-Inhibit exception */ 1537#define EXCCODE_TLBNX 6 /* TLB Execution-Inhibit exception */ 1538#define EXCCODE_TLBPE 7 /* TLB Privilege Error */ 1539#define EXCCODE_ADE 8 /* Address Error */ 1540 #define EXSUBCODE_ADEF 0 /* Fetch Instruction */ 1541 #define EXSUBCODE_ADEM 1 /* Access Memory*/ 1542#define EXCCODE_ALE 9 /* Unalign Access */ 1543#define EXCCODE_BCE 10 /* Bounds Check Error */ 1544#define EXCCODE_SYS 11 /* System call */ 1545#define EXCCODE_BP 12 /* Breakpoint */ 1546#define EXCCODE_INE 13 /* Inst. Not Exist */ 1547#define EXCCODE_IPE 14 /* Inst. Privileged Error */ 1548#define EXCCODE_FPDIS 15 /* FPU Disabled */ 1549#define EXCCODE_LSXDIS 16 /* LSX Disabled */ 1550#define EXCCODE_LASXDIS 17 /* LASX Disabled */ 1551#define EXCCODE_FPE 18 /* Floating Point Exception */ 1552 #define EXCSUBCODE_FPE 0 /* Floating Point Exception */ 1553 #define EXCSUBCODE_VFPE 1 /* Vector Exception */ 1554#define EXCCODE_WATCH 19 /* WatchPoint Exception */ 1555 #define EXCSUBCODE_WPEF 0 /* ... on Instruction Fetch */ 1556 #define EXCSUBCODE_WPEM 1 /* ... on Memory Accesses */ 1557#define EXCCODE_BTDIS 20 /* Binary Trans. Disabled */ 1558#define EXCCODE_BTE 21 /* Binary Trans. Exception */ 1559#define EXCCODE_GSPR 22 /* Guest Privileged Error */ 1560#define EXCCODE_HVC 23 /* Hypercall */ 1561#define EXCCODE_GCM 24 /* Guest CSR modified */ 1562 #define EXCSUBCODE_GCSC 0 /* Software caused */ 1563 #define EXCSUBCODE_GCHC 1 /* Hardware caused */ 1564#define EXCCODE_SE 25 /* Security */ 1565 1566/* Interrupt numbers */ 1567#define INT_SWI0 0 /* Software Interrupts */ 1568#define INT_SWI1 1 1569#define INT_HWI0 2 /* Hardware Interrupts */ 1570#define INT_HWI1 3 1571#define INT_HWI2 4 1572#define INT_HWI3 5 1573#define INT_HWI4 6 1574#define INT_HWI5 7 1575#define INT_HWI6 8 1576#define INT_HWI7 9 1577#define INT_PCOV 10 /* Performance Counter Overflow */ 1578#define INT_TI 11 /* Timer */ 1579#define INT_IPI 12 1580#define INT_NMI 13 1581 1582/* ExcCodes corresponding to interrupts */ 1583#define EXCCODE_INT_NUM (INT_NMI + 1) 1584#define EXCCODE_INT_START 64 1585#define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1) 1586 1587/* FPU register names */ 1588#define LOONGARCH_FCSR0 $r0 1589#define LOONGARCH_FCSR1 $r1 1590#define LOONGARCH_FCSR2 $r2 1591#define LOONGARCH_FCSR3 $r3 1592 1593/* FPU Status Register Values */ 1594#define FPU_CSR_RSVD 0xe0e0fce0 1595 1596/* 1597 * X the exception cause indicator 1598 * E the exception enable 1599 * S the sticky/flag bit 1600 */ 1601#define FPU_CSR_ALL_X 0x1f000000 1602#define FPU_CSR_INV_X 0x10000000 1603#define FPU_CSR_DIV_X 0x08000000 1604#define FPU_CSR_OVF_X 0x04000000 1605#define FPU_CSR_UDF_X 0x02000000 1606#define FPU_CSR_INE_X 0x01000000 1607 1608#define FPU_CSR_ALL_S 0x001f0000 1609#define FPU_CSR_INV_S 0x00100000 1610#define FPU_CSR_DIV_S 0x00080000 1611#define FPU_CSR_OVF_S 0x00040000 1612#define FPU_CSR_UDF_S 0x00020000 1613#define FPU_CSR_INE_S 0x00010000 1614 1615#define FPU_CSR_ALL_E 0x0000001f 1616#define FPU_CSR_INV_E 0x00000010 1617#define FPU_CSR_DIV_E 0x00000008 1618#define FPU_CSR_OVF_E 0x00000004 1619#define FPU_CSR_UDF_E 0x00000002 1620#define FPU_CSR_INE_E 0x00000001 1621 1622/* Bits 8 and 9 of FPU Status Register specify the rounding mode */ 1623#define FPU_CSR_RM 0x300 1624#define FPU_CSR_RN 0x000 /* nearest */ 1625#define FPU_CSR_RZ 0x100 /* towards zero */ 1626#define FPU_CSR_RU 0x200 /* towards +Infinity */ 1627#define FPU_CSR_RD 0x300 /* towards -Infinity */ 1628 1629/* LBT extension */ 1630#define FPU_CSR_TM_SHIFT 0x6 1631#define FPU_CSR_TM 0x40 /* float register in stack mode */ 1632 1633#define write_fcsr(dest, val) \ 1634do { \ 1635 __asm__ __volatile__( \ 1636 " movgr2fcsr "__stringify(dest)", %0 \n" \ 1637 : : "r" (val)); \ 1638} while (0) 1639 1640#define read_fcsr(source) \ 1641({ \ 1642 unsigned int __res; \ 1643\ 1644 __asm__ __volatile__( \ 1645 " movfcsr2gr %0, "__stringify(source)" \n" \ 1646 : "=r" (__res)); \ 1647 __res; \ 1648}) 1649 1650#endif /* _ASM_LOONGARCHREGS_H */ 1651