1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Loongson Technology Corporation Limited
4 */
5#ifndef __ASM_CPU_INFO_H
6#define __ASM_CPU_INFO_H
7
8#include <linux/cache.h>
9#include <linux/types.h>
10
11#include <asm/loongarchregs.h>
12
13/* cache_desc->flags */
14enum {
15	CACHE_PRESENT	= (1 << 0),
16	CACHE_PRIVATE	= (1 << 1),	/* core private cache */
17	CACHE_INCLUSIVE	= (1 << 2),	/* include the inner level caches */
18};
19
20/*
21 * Descriptor for a cache
22 */
23struct cache_desc {
24	unsigned char type;
25	unsigned char level;
26	unsigned short sets;	/* Number of lines per set */
27	unsigned char ways;	/* Number of ways */
28	unsigned char linesz;	/* Size of line in bytes */
29	unsigned char flags;	/* Flags describing cache properties */
30};
31
32#define CACHE_LEVEL_MAX		3
33#define CACHE_LEAVES_MAX	6
34
35struct guest_info {
36	unsigned long		ases;
37	unsigned long		ases_dyn;
38	unsigned long long	options;
39	unsigned long long	options_dyn;
40	u8			conf;
41	unsigned int		kscratch_mask;
42};
43
44struct cpuinfo_loongarch {
45	u64			asid_cache;
46	unsigned long		asid_mask;
47
48	/*
49	 * Capability and feature descriptor structure for LoongArch CPU
50	 */
51	unsigned long		ases;
52	unsigned long long	options;
53	unsigned int		processor_id;
54	unsigned int		fpu_vers;
55	unsigned int		fpu_csr0;
56	unsigned int		fpu_mask;
57	unsigned int		cputype;
58	int			isa_level;
59	int			tlbsize;
60	int			tlbsizemtlb;
61	int			tlbsizestlbsets;
62	int			tlbsizestlbways;
63	int			cache_leaves_present; /* number of cache_leaves[] elements */
64	struct cache_desc	cache_leaves[CACHE_LEAVES_MAX];
65	int			core;   /* physical core number in package */
66	int			package;/* physical package number */
67	int			global_id; /* physical global thread number */
68	int			vabits; /* Virtual Address size in bits */
69	int			pabits; /* Physical Address size in bits */
70	unsigned int		ksave_mask; /* Usable KSave mask. */
71	unsigned int		watch_dreg_count;   /* Number data breakpoints */
72	unsigned int		watch_ireg_count;   /* Number instruction breakpoints */
73	unsigned int		watch_reg_use_cnt; /* min(NUM_WATCH_REGS, watch_dreg_count + watch_ireg_count), Usable by ptrace */
74
75	/* VZ & Guest features */
76	struct guest_info	guest;
77	unsigned long		guest_cfg;
78} __attribute__((aligned(SMP_CACHE_BYTES)));
79
80extern struct cpuinfo_loongarch cpu_data[];
81#define boot_cpu_data cpu_data[0]
82#define current_cpu_data cpu_data[smp_processor_id()]
83#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
84
85extern void cpu_probe(void);
86
87extern const char *__cpu_family[];
88extern const char *__cpu_full_name[];
89#define cpu_family_string()	__cpu_family[raw_smp_processor_id()]
90#define cpu_full_name_string()	__cpu_full_name[raw_smp_processor_id()]
91
92struct seq_file;
93struct notifier_block;
94
95extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
96extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
97
98#define proc_cpuinfo_notifier(fn, pri)					\
99({									\
100	static struct notifier_block fn##_nb = {			\
101		.notifier_call = fn,					\
102		.priority = pri						\
103	};								\
104									\
105	register_proc_cpuinfo_notifier(&fn##_nb);			\
106})
107
108struct proc_cpuinfo_notifier_args {
109	struct seq_file *m;
110	unsigned long n;
111};
112
113static inline bool cpus_are_siblings(int cpua, int cpub)
114{
115	struct cpuinfo_loongarch *infoa = &cpu_data[cpua];
116	struct cpuinfo_loongarch *infob = &cpu_data[cpub];
117
118	if (infoa->package != infob->package)
119		return false;
120
121	if (infoa->core != infob->core)
122		return false;
123
124	return true;
125}
126
127static inline unsigned long cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo)
128{
129	return cpuinfo->asid_mask;
130}
131
132static inline void set_cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo,
133				     unsigned long asid_mask)
134{
135	cpuinfo->asid_mask = asid_mask;
136}
137
138#endif /* __ASM_CPU_INFO_H */
139