1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * This file contains the McKinley PMU register description tables 4 * and pmc checker used by perfmon.c. 5 * 6 * Copyright (C) 2002-2003 Hewlett Packard Co 7 * Stephane Eranian <eranian@hpl.hp.com> 8 */ 9static int pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs); 10 11static pfm_reg_desc_t pfm_mck_pmc_desc[PMU_MAX_PMCS]={ 12/* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 13/* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 14/* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 15/* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 16/* pmc4 */ { PFM_REG_COUNTING, 6, 0x0000000000800000UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 17/* pmc5 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 18/* pmc6 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 19/* pmc7 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 20/* pmc8 */ { PFM_REG_CONFIG , 0, 0xffffffff3fffffffUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 21/* pmc9 */ { PFM_REG_CONFIG , 0, 0xffffffff3ffffffcUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 22/* pmc10 */ { PFM_REG_MONITOR , 4, 0x0UL, 0xffffUL, NULL, pfm_mck_pmc_check, {RDEP(0)|RDEP(1),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 23/* pmc11 */ { PFM_REG_MONITOR , 6, 0x0UL, 0x30f01cf, NULL, pfm_mck_pmc_check, {RDEP(2)|RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 24/* pmc12 */ { PFM_REG_MONITOR , 6, 0x0UL, 0xffffUL, NULL, pfm_mck_pmc_check, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 25/* pmc13 */ { PFM_REG_CONFIG , 0, 0x00002078fefefefeUL, 0x1e00018181818UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 26/* pmc14 */ { PFM_REG_CONFIG , 0, 0x0db60db60db60db6UL, 0x2492UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 27/* pmc15 */ { PFM_REG_CONFIG , 0, 0x00000000fffffff0UL, 0xfUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, 28 { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */ 29}; 30 31static pfm_reg_desc_t pfm_mck_pmd_desc[PMU_MAX_PMDS]={ 32/* pmd0 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(1),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}}, 33/* pmd1 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(0),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}}, 34/* pmd2 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}}, 35/* pmd3 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}}, 36/* pmd4 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}}, 37/* pmd5 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}}, 38/* pmd6 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(6),0UL, 0UL, 0UL}}, 39/* pmd7 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(7),0UL, 0UL, 0UL}}, 40/* pmd8 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, 41/* pmd9 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, 42/* pmd10 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, 43/* pmd11 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, 44/* pmd12 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, 45/* pmd13 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, 46/* pmd14 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, 47/* pmd15 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, 48/* pmd16 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, 49/* pmd17 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(3),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}}, 50 { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */ 51}; 52 53/* 54 * PMC reserved fields must have their power-up values preserved 55 */ 56static int 57pfm_mck_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs) 58{ 59 unsigned long tmp1, tmp2, ival = *val; 60 61 /* remove reserved areas from user value */ 62 tmp1 = ival & PMC_RSVD_MASK(cnum); 63 64 /* get reserved fields values */ 65 tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum); 66 67 *val = tmp1 | tmp2; 68 69 DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n", 70 cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val)); 71 return 0; 72} 73 74/* 75 * task can be NULL if the context is unloaded 76 */ 77static int 78pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs) 79{ 80 int ret = 0, check_case1 = 0; 81 unsigned long val8 = 0, val14 = 0, val13 = 0; 82 int is_loaded; 83 84 /* first preserve the reserved fields */ 85 pfm_mck_reserved(cnum, val, regs); 86 87 /* sanitfy check */ 88 if (ctx == NULL) return -EINVAL; 89 90 is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED; 91 92 /* 93 * we must clear the debug registers if pmc13 has a value which enable 94 * memory pipeline event constraints. In this case we need to clear the 95 * the debug registers if they have not yet been accessed. This is required 96 * to avoid picking stale state. 97 * PMC13 is "active" if: 98 * one of the pmc13.cfg_dbrpXX field is different from 0x3 99 * AND 100 * at the corresponding pmc13.ena_dbrpXX is set. 101 */ 102 DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, *val, ctx->ctx_fl_using_dbreg, is_loaded)); 103 104 if (cnum == 13 && is_loaded 105 && (*val & 0x1e00000000000UL) && (*val & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) { 106 107 DPRINT(("pmc[%d]=0x%lx has active pmc13 settings, clearing dbr\n", cnum, *val)); 108 109 /* don't mix debug with perfmon */ 110 if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL; 111 112 /* 113 * a count of 0 will mark the debug registers as in use and also 114 * ensure that they are properly cleared. 115 */ 116 ret = pfm_write_ibr_dbr(PFM_DATA_RR, ctx, NULL, 0, regs); 117 if (ret) return ret; 118 } 119 /* 120 * we must clear the (instruction) debug registers if any pmc14.ibrpX bit is enabled 121 * before they are (fl_using_dbreg==0) to avoid picking up stale information. 122 */ 123 if (cnum == 14 && is_loaded && ((*val & 0x2222UL) != 0x2222UL) && ctx->ctx_fl_using_dbreg == 0) { 124 125 DPRINT(("pmc[%d]=0x%lx has active pmc14 settings, clearing ibr\n", cnum, *val)); 126 127 /* don't mix debug with perfmon */ 128 if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL; 129 130 /* 131 * a count of 0 will mark the debug registers as in use and also 132 * ensure that they are properly cleared. 133 */ 134 ret = pfm_write_ibr_dbr(PFM_CODE_RR, ctx, NULL, 0, regs); 135 if (ret) return ret; 136 137 } 138 139 switch(cnum) { 140 case 4: *val |= 1UL << 23; /* force power enable bit */ 141 break; 142 case 8: val8 = *val; 143 val13 = ctx->ctx_pmcs[13]; 144 val14 = ctx->ctx_pmcs[14]; 145 check_case1 = 1; 146 break; 147 case 13: val8 = ctx->ctx_pmcs[8]; 148 val13 = *val; 149 val14 = ctx->ctx_pmcs[14]; 150 check_case1 = 1; 151 break; 152 case 14: val8 = ctx->ctx_pmcs[8]; 153 val13 = ctx->ctx_pmcs[13]; 154 val14 = *val; 155 check_case1 = 1; 156 break; 157 } 158 /* check illegal configuration which can produce inconsistencies in tagging 159 * i-side events in L1D and L2 caches 160 */ 161 if (check_case1) { 162 ret = ((val13 >> 45) & 0xf) == 0 163 && ((val8 & 0x1) == 0) 164 && ((((val14>>1) & 0x3) == 0x2 || ((val14>>1) & 0x3) == 0x0) 165 ||(((val14>>4) & 0x3) == 0x2 || ((val14>>4) & 0x3) == 0x0)); 166 167 if (ret) DPRINT((KERN_DEBUG "perfmon: failure check_case1\n")); 168 } 169 170 return ret ? -EINVAL : 0; 171} 172 173/* 174 * impl_pmcs, impl_pmds are computed at runtime to minimize errors! 175 */ 176static pmu_config_t pmu_conf_mck={ 177 .pmu_name = "Itanium 2", 178 .pmu_family = 0x1f, 179 .flags = PFM_PMU_IRQ_RESEND, 180 .ovfl_val = (1UL << 47) - 1, 181 .pmd_desc = pfm_mck_pmd_desc, 182 .pmc_desc = pfm_mck_pmc_desc, 183 .num_ibrs = 8, 184 .num_dbrs = 8, 185 .use_rr_dbregs = 1 /* debug register are use for range restrictions */ 186}; 187 188 189