1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_IA64_PAL_H 3#define _ASM_IA64_PAL_H 4 5/* 6 * Processor Abstraction Layer definitions. 7 * 8 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0 9 * chapter 11 IA-64 Processor Abstraction Layer 10 * 11 * Copyright (C) 1998-2001 Hewlett-Packard Co 12 * David Mosberger-Tang <davidm@hpl.hp.com> 13 * Stephane Eranian <eranian@hpl.hp.com> 14 * Copyright (C) 1999 VA Linux Systems 15 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 16 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> 17 * Copyright (C) 2008 Silicon Graphics, Inc. (SGI) 18 * 19 * 99/10/01 davidm Make sure we pass zero for reserved parameters. 20 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6. 21 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info 22 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added 23 * 00/05/25 eranian Support for stack calls, and static physical calls 24 * 00/06/18 eranian Support for stacked physical calls 25 * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's 26 * Manual Rev 2.2 (Jan 2006) 27 */ 28 29/* 30 * Note that some of these calls use a static-register only calling 31 * convention which has nothing to do with the regular calling 32 * convention. 33 */ 34#define PAL_CACHE_FLUSH 1 /* flush i/d cache */ 35#define PAL_CACHE_INFO 2 /* get detailed i/d cache info */ 36#define PAL_CACHE_INIT 3 /* initialize i/d cache */ 37#define PAL_CACHE_SUMMARY 4 /* get summary of cache hierarchy */ 38#define PAL_MEM_ATTRIB 5 /* list supported memory attributes */ 39#define PAL_PTCE_INFO 6 /* purge TLB info */ 40#define PAL_VM_INFO 7 /* return supported virtual memory features */ 41#define PAL_VM_SUMMARY 8 /* return summary on supported vm features */ 42#define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */ 43#define PAL_BUS_SET_FEATURES 10 /* set processor bus features */ 44#define PAL_DEBUG_INFO 11 /* get number of debug registers */ 45#define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */ 46#define PAL_FREQ_BASE 13 /* base frequency of the platform */ 47#define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */ 48#define PAL_PERF_MON_INFO 15 /* return performance monitor info */ 49#define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */ 50#define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */ 51#define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */ 52#define PAL_RSE_INFO 19 /* return rse information */ 53#define PAL_VERSION 20 /* return version of PAL code */ 54#define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */ 55#define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */ 56#define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */ 57#define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */ 58#define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */ 59#define PAL_MC_RESUME 26 /* Return to interrupted process */ 60#define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */ 61#define PAL_HALT 28 /* enter the low power HALT state */ 62#define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/ 63#define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */ 64#define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */ 65#define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */ 66#define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */ 67#define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */ 68 69#define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */ 70#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */ 71#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/ 72#define PAL_SHUTDOWN 40 /* enter processor shutdown state */ 73#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */ 74#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */ 75#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */ 76#define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */ 77#define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */ 78#define PAL_VP_INFO 50 /* Information about virtual processor features */ 79#define PAL_MC_HW_TRACKING 51 /* Hardware tracking status */ 80 81#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */ 82#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */ 83#define PAL_TEST_PROC 258 /* perform late processor self-test */ 84#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */ 85#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */ 86#define PAL_VM_TR_READ 261 /* read contents of translation register */ 87#define PAL_GET_PSTATE 262 /* get the current P-state */ 88#define PAL_SET_PSTATE 263 /* set the P-state */ 89#define PAL_BRAND_INFO 274 /* Processor branding information */ 90 91#define PAL_GET_PSTATE_TYPE_LASTSET 0 92#define PAL_GET_PSTATE_TYPE_AVGANDRESET 1 93#define PAL_GET_PSTATE_TYPE_AVGNORESET 2 94#define PAL_GET_PSTATE_TYPE_INSTANT 3 95 96#define PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */ 97 98#ifndef __ASSEMBLY__ 99 100#include <linux/types.h> 101#include <asm/fpu.h> 102 103/* 104 * Data types needed to pass information into PAL procedures and 105 * interpret information returned by them. 106 */ 107 108/* Return status from the PAL procedure */ 109typedef s64 pal_status_t; 110 111#define PAL_STATUS_SUCCESS 0 /* No error */ 112#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */ 113#define PAL_STATUS_EINVAL (-2) /* Invalid argument */ 114#define PAL_STATUS_ERROR (-3) /* Error */ 115#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the 116 * specified level and type of 117 * cache without sideeffects 118 * and "restrict" was 1 119 */ 120#define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */ 121 122/* Processor cache level in the hierarchy */ 123typedef u64 pal_cache_level_t; 124#define PAL_CACHE_LEVEL_L0 0 /* L0 */ 125#define PAL_CACHE_LEVEL_L1 1 /* L1 */ 126#define PAL_CACHE_LEVEL_L2 2 /* L2 */ 127 128 129/* Processor cache type at a particular level in the hierarchy */ 130 131typedef u64 pal_cache_type_t; 132#define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */ 133#define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */ 134#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */ 135 136 137#define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */ 138#define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */ 139 140/* Processor cache line size in bytes */ 141typedef int pal_cache_line_size_t; 142 143/* Processor cache line state */ 144typedef u64 pal_cache_line_state_t; 145#define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */ 146#define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */ 147#define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */ 148#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */ 149 150typedef struct pal_freq_ratio { 151 u32 den, num; /* numerator & denominator */ 152} itc_ratio, proc_ratio; 153 154typedef union pal_cache_config_info_1_s { 155 struct { 156 u64 u : 1, /* 0 Unified cache ? */ 157 at : 2, /* 2-1 Cache mem attr*/ 158 reserved : 5, /* 7-3 Reserved */ 159 associativity : 8, /* 16-8 Associativity*/ 160 line_size : 8, /* 23-17 Line size */ 161 stride : 8, /* 31-24 Stride */ 162 store_latency : 8, /*39-32 Store latency*/ 163 load_latency : 8, /* 47-40 Load latency*/ 164 store_hints : 8, /* 55-48 Store hints*/ 165 load_hints : 8; /* 63-56 Load hints */ 166 } pcci1_bits; 167 u64 pcci1_data; 168} pal_cache_config_info_1_t; 169 170typedef union pal_cache_config_info_2_s { 171 struct { 172 u32 cache_size; /*cache size in bytes*/ 173 174 175 u32 alias_boundary : 8, /* 39-32 aliased addr 176 * separation for max 177 * performance. 178 */ 179 tag_ls_bit : 8, /* 47-40 LSb of addr*/ 180 tag_ms_bit : 8, /* 55-48 MSb of addr*/ 181 reserved : 8; /* 63-56 Reserved */ 182 } pcci2_bits; 183 u64 pcci2_data; 184} pal_cache_config_info_2_t; 185 186 187typedef struct pal_cache_config_info_s { 188 pal_status_t pcci_status; 189 pal_cache_config_info_1_t pcci_info_1; 190 pal_cache_config_info_2_t pcci_info_2; 191 u64 pcci_reserved; 192} pal_cache_config_info_t; 193 194#define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints 195#define pcci_st_hints pcci_info_1.pcci1_bits.store_hints 196#define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency 197#define pcci_st_latency pcci_info_1.pcci1_bits.store_latency 198#define pcci_stride pcci_info_1.pcci1_bits.stride 199#define pcci_line_size pcci_info_1.pcci1_bits.line_size 200#define pcci_assoc pcci_info_1.pcci1_bits.associativity 201#define pcci_cache_attr pcci_info_1.pcci1_bits.at 202#define pcci_unified pcci_info_1.pcci1_bits.u 203#define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit 204#define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit 205#define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary 206#define pcci_cache_size pcci_info_2.pcci2_bits.cache_size 207 208 209 210/* Possible values for cache attributes */ 211 212#define PAL_CACHE_ATTR_WT 0 /* Write through cache */ 213#define PAL_CACHE_ATTR_WB 1 /* Write back cache */ 214#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write 215 * back depending on TLB 216 * memory attributes 217 */ 218 219 220/* Possible values for cache hints */ 221 222#define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */ 223#define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */ 224#define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */ 225 226/* Processor cache protection information */ 227typedef union pal_cache_protection_element_u { 228 u32 pcpi_data; 229 struct { 230 u32 data_bits : 8, /* # data bits covered by 231 * each unit of protection 232 */ 233 234 tagprot_lsb : 6, /* Least -do- */ 235 tagprot_msb : 6, /* Most Sig. tag address 236 * bit that this 237 * protection covers. 238 */ 239 prot_bits : 6, /* # of protection bits */ 240 method : 4, /* Protection method */ 241 t_d : 2; /* Indicates which part 242 * of the cache this 243 * protection encoding 244 * applies. 245 */ 246 } pcp_info; 247} pal_cache_protection_element_t; 248 249#define pcpi_cache_prot_part pcp_info.t_d 250#define pcpi_prot_method pcp_info.method 251#define pcpi_prot_bits pcp_info.prot_bits 252#define pcpi_tagprot_msb pcp_info.tagprot_msb 253#define pcpi_tagprot_lsb pcp_info.tagprot_lsb 254#define pcpi_data_bits pcp_info.data_bits 255 256/* Processor cache part encodings */ 257#define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */ 258#define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */ 259#define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is 260 * more significant ) 261 */ 262#define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is 263 * more significant ) 264 */ 265#define PAL_CACHE_PROT_PART_MAX 6 266 267 268typedef struct pal_cache_protection_info_s { 269 pal_status_t pcpi_status; 270 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX]; 271} pal_cache_protection_info_t; 272 273 274/* Processor cache protection method encodings */ 275#define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */ 276#define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */ 277#define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */ 278#define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */ 279 280 281/* Processor cache line identification in the hierarchy */ 282typedef union pal_cache_line_id_u { 283 u64 pclid_data; 284 struct { 285 u64 cache_type : 8, /* 7-0 cache type */ 286 level : 8, /* 15-8 level of the 287 * cache in the 288 * hierarchy. 289 */ 290 way : 8, /* 23-16 way in the set 291 */ 292 part : 8, /* 31-24 part of the 293 * cache 294 */ 295 reserved : 32; /* 63-32 is reserved*/ 296 } pclid_info_read; 297 struct { 298 u64 cache_type : 8, /* 7-0 cache type */ 299 level : 8, /* 15-8 level of the 300 * cache in the 301 * hierarchy. 302 */ 303 way : 8, /* 23-16 way in the set 304 */ 305 part : 8, /* 31-24 part of the 306 * cache 307 */ 308 mesi : 8, /* 39-32 cache line 309 * state 310 */ 311 start : 8, /* 47-40 lsb of data to 312 * invert 313 */ 314 length : 8, /* 55-48 #bits to 315 * invert 316 */ 317 trigger : 8; /* 63-56 Trigger error 318 * by doing a load 319 * after the write 320 */ 321 322 } pclid_info_write; 323} pal_cache_line_id_u_t; 324 325#define pclid_read_part pclid_info_read.part 326#define pclid_read_way pclid_info_read.way 327#define pclid_read_level pclid_info_read.level 328#define pclid_read_cache_type pclid_info_read.cache_type 329 330#define pclid_write_trigger pclid_info_write.trigger 331#define pclid_write_length pclid_info_write.length 332#define pclid_write_start pclid_info_write.start 333#define pclid_write_mesi pclid_info_write.mesi 334#define pclid_write_part pclid_info_write.part 335#define pclid_write_way pclid_info_write.way 336#define pclid_write_level pclid_info_write.level 337#define pclid_write_cache_type pclid_info_write.cache_type 338 339/* Processor cache line part encodings */ 340#define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */ 341#define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */ 342#define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */ 343#define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */ 344#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag 345 * protection 346 */ 347typedef struct pal_cache_line_info_s { 348 pal_status_t pcli_status; /* Return status of the read cache line 349 * info call. 350 */ 351 u64 pcli_data; /* 64-bit data, tag, protection bits .. */ 352 u64 pcli_data_len; /* data length in bits */ 353 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */ 354 355} pal_cache_line_info_t; 356 357 358/* Machine Check related crap */ 359 360/* Pending event status bits */ 361typedef u64 pal_mc_pending_events_t; 362 363#define PAL_MC_PENDING_MCA (1 << 0) 364#define PAL_MC_PENDING_INIT (1 << 1) 365 366/* Error information type */ 367typedef u64 pal_mc_info_index_t; 368 369#define PAL_MC_INFO_PROCESSOR 0 /* Processor */ 370#define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */ 371#define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */ 372#define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */ 373#define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */ 374#define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */ 375#define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */ 376#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation 377 * dependent 378 */ 379 380#define PAL_TLB_CHECK_OP_PURGE 8 381 382typedef struct pal_process_state_info_s { 383 u64 reserved1 : 2, 384 rz : 1, /* PAL_CHECK processor 385 * rendezvous 386 * successful. 387 */ 388 389 ra : 1, /* PAL_CHECK attempted 390 * a rendezvous. 391 */ 392 me : 1, /* Distinct multiple 393 * errors occurred 394 */ 395 396 mn : 1, /* Min. state save 397 * area has been 398 * registered with PAL 399 */ 400 401 sy : 1, /* Storage integrity 402 * synched 403 */ 404 405 406 co : 1, /* Continuable */ 407 ci : 1, /* MC isolated */ 408 us : 1, /* Uncontained storage 409 * damage. 410 */ 411 412 413 hd : 1, /* Non-essential hw 414 * lost (no loss of 415 * functionality) 416 * causing the 417 * processor to run in 418 * degraded mode. 419 */ 420 421 tl : 1, /* 1 => MC occurred 422 * after an instr was 423 * executed but before 424 * the trap that 425 * resulted from instr 426 * execution was 427 * generated. 428 * (Trap Lost ) 429 */ 430 mi : 1, /* More information available 431 * call PAL_MC_ERROR_INFO 432 */ 433 pi : 1, /* Precise instruction pointer */ 434 pm : 1, /* Precise min-state save area */ 435 436 dy : 1, /* Processor dynamic 437 * state valid 438 */ 439 440 441 in : 1, /* 0 = MC, 1 = INIT */ 442 rs : 1, /* RSE valid */ 443 cm : 1, /* MC corrected */ 444 ex : 1, /* MC is expected */ 445 cr : 1, /* Control regs valid*/ 446 pc : 1, /* Perf cntrs valid */ 447 dr : 1, /* Debug regs valid */ 448 tr : 1, /* Translation regs 449 * valid 450 */ 451 rr : 1, /* Region regs valid */ 452 ar : 1, /* App regs valid */ 453 br : 1, /* Branch regs valid */ 454 pr : 1, /* Predicate registers 455 * valid 456 */ 457 458 fp : 1, /* fp registers valid*/ 459 b1 : 1, /* Preserved bank one 460 * general registers 461 * are valid 462 */ 463 b0 : 1, /* Preserved bank zero 464 * general registers 465 * are valid 466 */ 467 gr : 1, /* General registers 468 * are valid 469 * (excl. banked regs) 470 */ 471 dsize : 16, /* size of dynamic 472 * state returned 473 * by the processor 474 */ 475 476 se : 1, /* Shared error. MCA in a 477 shared structure */ 478 reserved2 : 10, 479 cc : 1, /* Cache check */ 480 tc : 1, /* TLB check */ 481 bc : 1, /* Bus check */ 482 rc : 1, /* Register file check */ 483 uc : 1; /* Uarch check */ 484 485} pal_processor_state_info_t; 486 487typedef struct pal_cache_check_info_s { 488 u64 op : 4, /* Type of cache 489 * operation that 490 * caused the machine 491 * check. 492 */ 493 level : 2, /* Cache level */ 494 reserved1 : 2, 495 dl : 1, /* Failure in data part 496 * of cache line 497 */ 498 tl : 1, /* Failure in tag part 499 * of cache line 500 */ 501 dc : 1, /* Failure in dcache */ 502 ic : 1, /* Failure in icache */ 503 mesi : 3, /* Cache line state */ 504 mv : 1, /* mesi valid */ 505 way : 5, /* Way in which the 506 * error occurred 507 */ 508 wiv : 1, /* Way field valid */ 509 reserved2 : 1, 510 dp : 1, /* Data poisoned on MBE */ 511 reserved3 : 6, 512 hlth : 2, /* Health indicator */ 513 514 index : 20, /* Cache line index */ 515 reserved4 : 2, 516 517 is : 1, /* instruction set (1 == ia32) */ 518 iv : 1, /* instruction set field valid */ 519 pl : 2, /* privilege level */ 520 pv : 1, /* privilege level field valid */ 521 mcc : 1, /* Machine check corrected */ 522 tv : 1, /* Target address 523 * structure is valid 524 */ 525 rq : 1, /* Requester identifier 526 * structure is valid 527 */ 528 rp : 1, /* Responder identifier 529 * structure is valid 530 */ 531 pi : 1; /* Precise instruction pointer 532 * structure is valid 533 */ 534} pal_cache_check_info_t; 535 536typedef struct pal_tlb_check_info_s { 537 538 u64 tr_slot : 8, /* Slot# of TR where 539 * error occurred 540 */ 541 trv : 1, /* tr_slot field is valid */ 542 reserved1 : 1, 543 level : 2, /* TLB level where failure occurred */ 544 reserved2 : 4, 545 dtr : 1, /* Fail in data TR */ 546 itr : 1, /* Fail in inst TR */ 547 dtc : 1, /* Fail in data TC */ 548 itc : 1, /* Fail in inst. TC */ 549 op : 4, /* Cache operation */ 550 reserved3 : 6, 551 hlth : 2, /* Health indicator */ 552 reserved4 : 22, 553 554 is : 1, /* instruction set (1 == ia32) */ 555 iv : 1, /* instruction set field valid */ 556 pl : 2, /* privilege level */ 557 pv : 1, /* privilege level field valid */ 558 mcc : 1, /* Machine check corrected */ 559 tv : 1, /* Target address 560 * structure is valid 561 */ 562 rq : 1, /* Requester identifier 563 * structure is valid 564 */ 565 rp : 1, /* Responder identifier 566 * structure is valid 567 */ 568 pi : 1; /* Precise instruction pointer 569 * structure is valid 570 */ 571} pal_tlb_check_info_t; 572 573typedef struct pal_bus_check_info_s { 574 u64 size : 5, /* Xaction size */ 575 ib : 1, /* Internal bus error */ 576 eb : 1, /* External bus error */ 577 cc : 1, /* Error occurred 578 * during cache-cache 579 * transfer. 580 */ 581 type : 8, /* Bus xaction type*/ 582 sev : 5, /* Bus error severity*/ 583 hier : 2, /* Bus hierarchy level */ 584 dp : 1, /* Data poisoned on MBE */ 585 bsi : 8, /* Bus error status 586 * info 587 */ 588 reserved2 : 22, 589 590 is : 1, /* instruction set (1 == ia32) */ 591 iv : 1, /* instruction set field valid */ 592 pl : 2, /* privilege level */ 593 pv : 1, /* privilege level field valid */ 594 mcc : 1, /* Machine check corrected */ 595 tv : 1, /* Target address 596 * structure is valid 597 */ 598 rq : 1, /* Requester identifier 599 * structure is valid 600 */ 601 rp : 1, /* Responder identifier 602 * structure is valid 603 */ 604 pi : 1; /* Precise instruction pointer 605 * structure is valid 606 */ 607} pal_bus_check_info_t; 608 609typedef struct pal_reg_file_check_info_s { 610 u64 id : 4, /* Register file identifier */ 611 op : 4, /* Type of register 612 * operation that 613 * caused the machine 614 * check. 615 */ 616 reg_num : 7, /* Register number */ 617 rnv : 1, /* reg_num valid */ 618 reserved2 : 38, 619 620 is : 1, /* instruction set (1 == ia32) */ 621 iv : 1, /* instruction set field valid */ 622 pl : 2, /* privilege level */ 623 pv : 1, /* privilege level field valid */ 624 mcc : 1, /* Machine check corrected */ 625 reserved3 : 3, 626 pi : 1; /* Precise instruction pointer 627 * structure is valid 628 */ 629} pal_reg_file_check_info_t; 630 631typedef struct pal_uarch_check_info_s { 632 u64 sid : 5, /* Structure identification */ 633 level : 3, /* Level of failure */ 634 array_id : 4, /* Array identification */ 635 op : 4, /* Type of 636 * operation that 637 * caused the machine 638 * check. 639 */ 640 way : 6, /* Way of structure */ 641 wv : 1, /* way valid */ 642 xv : 1, /* index valid */ 643 reserved1 : 6, 644 hlth : 2, /* Health indicator */ 645 index : 8, /* Index or set of the uarch 646 * structure that failed. 647 */ 648 reserved2 : 24, 649 650 is : 1, /* instruction set (1 == ia32) */ 651 iv : 1, /* instruction set field valid */ 652 pl : 2, /* privilege level */ 653 pv : 1, /* privilege level field valid */ 654 mcc : 1, /* Machine check corrected */ 655 tv : 1, /* Target address 656 * structure is valid 657 */ 658 rq : 1, /* Requester identifier 659 * structure is valid 660 */ 661 rp : 1, /* Responder identifier 662 * structure is valid 663 */ 664 pi : 1; /* Precise instruction pointer 665 * structure is valid 666 */ 667} pal_uarch_check_info_t; 668 669typedef union pal_mc_error_info_u { 670 u64 pmei_data; 671 pal_processor_state_info_t pme_processor; 672 pal_cache_check_info_t pme_cache; 673 pal_tlb_check_info_t pme_tlb; 674 pal_bus_check_info_t pme_bus; 675 pal_reg_file_check_info_t pme_reg_file; 676 pal_uarch_check_info_t pme_uarch; 677} pal_mc_error_info_t; 678 679#define pmci_proc_unknown_check pme_processor.uc 680#define pmci_proc_bus_check pme_processor.bc 681#define pmci_proc_tlb_check pme_processor.tc 682#define pmci_proc_cache_check pme_processor.cc 683#define pmci_proc_dynamic_state_size pme_processor.dsize 684#define pmci_proc_gpr_valid pme_processor.gr 685#define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0 686#define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1 687#define pmci_proc_fp_valid pme_processor.fp 688#define pmci_proc_predicate_regs_valid pme_processor.pr 689#define pmci_proc_branch_regs_valid pme_processor.br 690#define pmci_proc_app_regs_valid pme_processor.ar 691#define pmci_proc_region_regs_valid pme_processor.rr 692#define pmci_proc_translation_regs_valid pme_processor.tr 693#define pmci_proc_debug_regs_valid pme_processor.dr 694#define pmci_proc_perf_counters_valid pme_processor.pc 695#define pmci_proc_control_regs_valid pme_processor.cr 696#define pmci_proc_machine_check_expected pme_processor.ex 697#define pmci_proc_machine_check_corrected pme_processor.cm 698#define pmci_proc_rse_valid pme_processor.rs 699#define pmci_proc_machine_check_or_init pme_processor.in 700#define pmci_proc_dynamic_state_valid pme_processor.dy 701#define pmci_proc_operation pme_processor.op 702#define pmci_proc_trap_lost pme_processor.tl 703#define pmci_proc_hardware_damage pme_processor.hd 704#define pmci_proc_uncontained_storage_damage pme_processor.us 705#define pmci_proc_machine_check_isolated pme_processor.ci 706#define pmci_proc_continuable pme_processor.co 707#define pmci_proc_storage_intergrity_synced pme_processor.sy 708#define pmci_proc_min_state_save_area_regd pme_processor.mn 709#define pmci_proc_distinct_multiple_errors pme_processor.me 710#define pmci_proc_pal_attempted_rendezvous pme_processor.ra 711#define pmci_proc_pal_rendezvous_complete pme_processor.rz 712 713 714#define pmci_cache_level pme_cache.level 715#define pmci_cache_line_state pme_cache.mesi 716#define pmci_cache_line_state_valid pme_cache.mv 717#define pmci_cache_line_index pme_cache.index 718#define pmci_cache_instr_cache_fail pme_cache.ic 719#define pmci_cache_data_cache_fail pme_cache.dc 720#define pmci_cache_line_tag_fail pme_cache.tl 721#define pmci_cache_line_data_fail pme_cache.dl 722#define pmci_cache_operation pme_cache.op 723#define pmci_cache_way_valid pme_cache.wv 724#define pmci_cache_target_address_valid pme_cache.tv 725#define pmci_cache_way pme_cache.way 726#define pmci_cache_mc pme_cache.mc 727 728#define pmci_tlb_instr_translation_cache_fail pme_tlb.itc 729#define pmci_tlb_data_translation_cache_fail pme_tlb.dtc 730#define pmci_tlb_instr_translation_reg_fail pme_tlb.itr 731#define pmci_tlb_data_translation_reg_fail pme_tlb.dtr 732#define pmci_tlb_translation_reg_slot pme_tlb.tr_slot 733#define pmci_tlb_mc pme_tlb.mc 734 735#define pmci_bus_status_info pme_bus.bsi 736#define pmci_bus_req_address_valid pme_bus.rq 737#define pmci_bus_resp_address_valid pme_bus.rp 738#define pmci_bus_target_address_valid pme_bus.tv 739#define pmci_bus_error_severity pme_bus.sev 740#define pmci_bus_transaction_type pme_bus.type 741#define pmci_bus_cache_cache_transfer pme_bus.cc 742#define pmci_bus_transaction_size pme_bus.size 743#define pmci_bus_internal_error pme_bus.ib 744#define pmci_bus_external_error pme_bus.eb 745#define pmci_bus_mc pme_bus.mc 746 747/* 748 * NOTE: this min_state_save area struct only includes the 1KB 749 * architectural state save area. The other 3 KB is scratch space 750 * for PAL. 751 */ 752 753typedef struct pal_min_state_area_s { 754 u64 pmsa_nat_bits; /* nat bits for saved GRs */ 755 u64 pmsa_gr[15]; /* GR1 - GR15 */ 756 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */ 757 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */ 758 u64 pmsa_pr; /* predicate registers */ 759 u64 pmsa_br0; /* branch register 0 */ 760 u64 pmsa_rsc; /* ar.rsc */ 761 u64 pmsa_iip; /* cr.iip */ 762 u64 pmsa_ipsr; /* cr.ipsr */ 763 u64 pmsa_ifs; /* cr.ifs */ 764 u64 pmsa_xip; /* previous iip */ 765 u64 pmsa_xpsr; /* previous psr */ 766 u64 pmsa_xfs; /* previous ifs */ 767 u64 pmsa_br1; /* branch register 1 */ 768 u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */ 769} pal_min_state_area_t; 770 771 772struct ia64_pal_retval { 773 /* 774 * A zero status value indicates call completed without error. 775 * A negative status value indicates reason of call failure. 776 * A positive status value indicates success but an 777 * informational value should be printed (e.g., "reboot for 778 * change to take effect"). 779 */ 780 s64 status; 781 u64 v0; 782 u64 v1; 783 u64 v2; 784}; 785 786/* 787 * Note: Currently unused PAL arguments are generally labeled 788 * "reserved" so the value specified in the PAL documentation 789 * (generally 0) MUST be passed. Reserved parameters are not optional 790 * parameters. 791 */ 792extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64); 793extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64); 794extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64); 795extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64); 796extern void ia64_save_scratch_fpregs (struct ia64_fpreg *); 797extern void ia64_load_scratch_fpregs (struct ia64_fpreg *); 798 799#define PAL_CALL(iprv,a0,a1,a2,a3) do { \ 800 struct ia64_fpreg fr[6]; \ 801 ia64_save_scratch_fpregs(fr); \ 802 iprv = ia64_pal_call_static(a0, a1, a2, a3); \ 803 ia64_load_scratch_fpregs(fr); \ 804} while (0) 805 806#define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \ 807 struct ia64_fpreg fr[6]; \ 808 ia64_save_scratch_fpregs(fr); \ 809 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \ 810 ia64_load_scratch_fpregs(fr); \ 811} while (0) 812 813#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \ 814 struct ia64_fpreg fr[6]; \ 815 ia64_save_scratch_fpregs(fr); \ 816 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \ 817 ia64_load_scratch_fpregs(fr); \ 818} while (0) 819 820#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \ 821 struct ia64_fpreg fr[6]; \ 822 ia64_save_scratch_fpregs(fr); \ 823 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \ 824 ia64_load_scratch_fpregs(fr); \ 825} while (0) 826 827typedef int (*ia64_pal_handler) (u64, ...); 828extern ia64_pal_handler ia64_pal; 829extern void ia64_pal_handler_init (void *); 830 831extern ia64_pal_handler ia64_pal; 832 833extern pal_cache_config_info_t l0d_cache_config_info; 834extern pal_cache_config_info_t l0i_cache_config_info; 835extern pal_cache_config_info_t l1_cache_config_info; 836extern pal_cache_config_info_t l2_cache_config_info; 837 838extern pal_cache_protection_info_t l0d_cache_protection_info; 839extern pal_cache_protection_info_t l0i_cache_protection_info; 840extern pal_cache_protection_info_t l1_cache_protection_info; 841extern pal_cache_protection_info_t l2_cache_protection_info; 842 843extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t, 844 pal_cache_type_t); 845 846extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t, 847 pal_cache_type_t); 848 849 850extern void pal_error(int); 851 852 853/* Useful wrappers for the current list of pal procedures */ 854 855typedef union pal_bus_features_u { 856 u64 pal_bus_features_val; 857 struct { 858 u64 pbf_reserved1 : 29; 859 u64 pbf_req_bus_parking : 1; 860 u64 pbf_bus_lock_mask : 1; 861 u64 pbf_enable_half_xfer_rate : 1; 862 u64 pbf_reserved2 : 20; 863 u64 pbf_enable_shared_line_replace : 1; 864 u64 pbf_enable_exclusive_line_replace : 1; 865 u64 pbf_disable_xaction_queueing : 1; 866 u64 pbf_disable_resp_err_check : 1; 867 u64 pbf_disable_berr_check : 1; 868 u64 pbf_disable_bus_req_internal_err_signal : 1; 869 u64 pbf_disable_bus_req_berr_signal : 1; 870 u64 pbf_disable_bus_init_event_check : 1; 871 u64 pbf_disable_bus_init_event_signal : 1; 872 u64 pbf_disable_bus_addr_err_check : 1; 873 u64 pbf_disable_bus_addr_err_signal : 1; 874 u64 pbf_disable_bus_data_err_check : 1; 875 } pal_bus_features_s; 876} pal_bus_features_u_t; 877 878extern void pal_bus_features_print (u64); 879 880/* Provide information about configurable processor bus features */ 881static inline s64 882ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail, 883 pal_bus_features_u_t *features_status, 884 pal_bus_features_u_t *features_control) 885{ 886 struct ia64_pal_retval iprv; 887 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0); 888 if (features_avail) 889 features_avail->pal_bus_features_val = iprv.v0; 890 if (features_status) 891 features_status->pal_bus_features_val = iprv.v1; 892 if (features_control) 893 features_control->pal_bus_features_val = iprv.v2; 894 return iprv.status; 895} 896 897/* Enables/disables specific processor bus features */ 898static inline s64 899ia64_pal_bus_set_features (pal_bus_features_u_t feature_select) 900{ 901 struct ia64_pal_retval iprv; 902 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0); 903 return iprv.status; 904} 905 906/* Get detailed cache information */ 907static inline s64 908ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf) 909{ 910 struct ia64_pal_retval iprv; 911 912 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0); 913 914 if (iprv.status == 0) { 915 conf->pcci_status = iprv.status; 916 conf->pcci_info_1.pcci1_data = iprv.v0; 917 conf->pcci_info_2.pcci2_data = iprv.v1; 918 conf->pcci_reserved = iprv.v2; 919 } 920 return iprv.status; 921 922} 923 924/* Get detailed cche protection information */ 925static inline s64 926ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot) 927{ 928 struct ia64_pal_retval iprv; 929 930 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0); 931 932 if (iprv.status == 0) { 933 prot->pcpi_status = iprv.status; 934 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; 935 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; 936 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff; 937 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32; 938 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff; 939 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32; 940 } 941 return iprv.status; 942} 943 944/* 945 * Flush the processor instruction or data caches. *PROGRESS must be 946 * initialized to zero before calling this for the first time.. 947 */ 948static inline s64 949ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector) 950{ 951 struct ia64_pal_retval iprv; 952 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); 953 if (vector) 954 *vector = iprv.v0; 955 *progress = iprv.v1; 956 return iprv.status; 957} 958 959 960/* Initialize the processor controlled caches */ 961static inline s64 962ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest) 963{ 964 struct ia64_pal_retval iprv; 965 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest); 966 return iprv.status; 967} 968 969/* Initialize the tags and data of a data or unified cache line of 970 * processor controlled cache to known values without the availability 971 * of backing memory. 972 */ 973static inline s64 974ia64_pal_cache_line_init (u64 physical_addr, u64 data_value) 975{ 976 struct ia64_pal_retval iprv; 977 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0); 978 return iprv.status; 979} 980 981 982/* Read the data and tag of a processor controlled cache line for diags */ 983static inline s64 984ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr) 985{ 986 struct ia64_pal_retval iprv; 987 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data, 988 physical_addr, 0); 989 return iprv.status; 990} 991 992/* Return summary information about the hierarchy of caches controlled by the processor */ 993static inline long ia64_pal_cache_summary(unsigned long *cache_levels, 994 unsigned long *unique_caches) 995{ 996 struct ia64_pal_retval iprv; 997 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0); 998 if (cache_levels) 999 *cache_levels = iprv.v0; 1000 if (unique_caches) 1001 *unique_caches = iprv.v1; 1002 return iprv.status; 1003} 1004 1005/* Write the data and tag of a processor-controlled cache line for diags */ 1006static inline s64 1007ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data) 1008{ 1009 struct ia64_pal_retval iprv; 1010 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data, 1011 physical_addr, data); 1012 return iprv.status; 1013} 1014 1015 1016/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */ 1017static inline s64 1018ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics, 1019 u64 *buffer_size, u64 *buffer_align) 1020{ 1021 struct ia64_pal_retval iprv; 1022 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics); 1023 if (buffer_size) 1024 *buffer_size = iprv.v0; 1025 if (buffer_align) 1026 *buffer_align = iprv.v1; 1027 return iprv.status; 1028} 1029 1030/* Copy relocatable PAL procedures from ROM to memory */ 1031static inline s64 1032ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset) 1033{ 1034 struct ia64_pal_retval iprv; 1035 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor); 1036 if (pal_proc_offset) 1037 *pal_proc_offset = iprv.v0; 1038 return iprv.status; 1039} 1040 1041/* Return the number of instruction and data debug register pairs */ 1042static inline long ia64_pal_debug_info(unsigned long *inst_regs, 1043 unsigned long *data_regs) 1044{ 1045 struct ia64_pal_retval iprv; 1046 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0); 1047 if (inst_regs) 1048 *inst_regs = iprv.v0; 1049 if (data_regs) 1050 *data_regs = iprv.v1; 1051 1052 return iprv.status; 1053} 1054 1055#ifdef TBD 1056/* Switch from IA64-system environment to IA-32 system environment */ 1057static inline s64 1058ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3) 1059{ 1060 struct ia64_pal_retval iprv; 1061 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3); 1062 return iprv.status; 1063} 1064#endif 1065 1066/* Get unique geographical address of this processor on its bus */ 1067static inline s64 1068ia64_pal_fixed_addr (u64 *global_unique_addr) 1069{ 1070 struct ia64_pal_retval iprv; 1071 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0); 1072 if (global_unique_addr) 1073 *global_unique_addr = iprv.v0; 1074 return iprv.status; 1075} 1076 1077/* Get base frequency of the platform if generated by the processor */ 1078static inline long ia64_pal_freq_base(unsigned long *platform_base_freq) 1079{ 1080 struct ia64_pal_retval iprv; 1081 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0); 1082 if (platform_base_freq) 1083 *platform_base_freq = iprv.v0; 1084 return iprv.status; 1085} 1086 1087/* 1088 * Get the ratios for processor frequency, bus frequency and interval timer to 1089 * to base frequency of the platform 1090 */ 1091static inline s64 1092ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio, 1093 struct pal_freq_ratio *itc_ratio) 1094{ 1095 struct ia64_pal_retval iprv; 1096 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0); 1097 if (proc_ratio) 1098 *(u64 *)proc_ratio = iprv.v0; 1099 if (bus_ratio) 1100 *(u64 *)bus_ratio = iprv.v1; 1101 if (itc_ratio) 1102 *(u64 *)itc_ratio = iprv.v2; 1103 return iprv.status; 1104} 1105 1106/* 1107 * Get the current hardware resource sharing policy of the processor 1108 */ 1109static inline s64 1110ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted, 1111 u64 *la) 1112{ 1113 struct ia64_pal_retval iprv; 1114 PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0); 1115 if (cur_policy) 1116 *cur_policy = iprv.v0; 1117 if (num_impacted) 1118 *num_impacted = iprv.v1; 1119 if (la) 1120 *la = iprv.v2; 1121 return iprv.status; 1122} 1123 1124/* Make the processor enter HALT or one of the implementation dependent low 1125 * power states where prefetching and execution are suspended and cache and 1126 * TLB coherency is not maintained. 1127 */ 1128static inline s64 1129ia64_pal_halt (u64 halt_state) 1130{ 1131 struct ia64_pal_retval iprv; 1132 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0); 1133 return iprv.status; 1134} 1135 1136typedef union pal_power_mgmt_info_u { 1137 u64 ppmi_data; 1138 struct { 1139 u64 exit_latency : 16, 1140 entry_latency : 16, 1141 power_consumption : 28, 1142 im : 1, 1143 co : 1, 1144 reserved : 2; 1145 } pal_power_mgmt_info_s; 1146} pal_power_mgmt_info_u_t; 1147 1148/* Return information about processor's optional power management capabilities. */ 1149static inline s64 1150ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) 1151{ 1152 struct ia64_pal_retval iprv; 1153 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0); 1154 return iprv.status; 1155} 1156 1157/* Get the current P-state information */ 1158static inline s64 1159ia64_pal_get_pstate (u64 *pstate_index, unsigned long type) 1160{ 1161 struct ia64_pal_retval iprv; 1162 PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0); 1163 *pstate_index = iprv.v0; 1164 return iprv.status; 1165} 1166 1167/* Set the P-state */ 1168static inline s64 1169ia64_pal_set_pstate (u64 pstate_index) 1170{ 1171 struct ia64_pal_retval iprv; 1172 PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0); 1173 return iprv.status; 1174} 1175 1176/* Processor branding information*/ 1177static inline s64 1178ia64_pal_get_brand_info (char *brand_info) 1179{ 1180 struct ia64_pal_retval iprv; 1181 PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0); 1182 return iprv.status; 1183} 1184 1185/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are 1186 * suspended, but cache and TLB coherency is maintained. 1187 */ 1188static inline s64 1189ia64_pal_halt_light (void) 1190{ 1191 struct ia64_pal_retval iprv; 1192 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0); 1193 return iprv.status; 1194} 1195 1196/* Clear all the processor error logging registers and reset the indicator that allows 1197 * the error logging registers to be written. This procedure also checks the pending 1198 * machine check bit and pending INIT bit and reports their states. 1199 */ 1200static inline s64 1201ia64_pal_mc_clear_log (u64 *pending_vector) 1202{ 1203 struct ia64_pal_retval iprv; 1204 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0); 1205 if (pending_vector) 1206 *pending_vector = iprv.v0; 1207 return iprv.status; 1208} 1209 1210/* Ensure that all outstanding transactions in a processor are completed or that any 1211 * MCA due to thes outstanding transaction is taken. 1212 */ 1213static inline s64 1214ia64_pal_mc_drain (void) 1215{ 1216 struct ia64_pal_retval iprv; 1217 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0); 1218 return iprv.status; 1219} 1220 1221/* Return the machine check dynamic processor state */ 1222static inline s64 1223ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size) 1224{ 1225 struct ia64_pal_retval iprv; 1226 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0); 1227 if (size) 1228 *size = iprv.v0; 1229 return iprv.status; 1230} 1231 1232/* Return processor machine check information */ 1233static inline s64 1234ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info) 1235{ 1236 struct ia64_pal_retval iprv; 1237 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0); 1238 if (size) 1239 *size = iprv.v0; 1240 if (error_info) 1241 *error_info = iprv.v1; 1242 return iprv.status; 1243} 1244 1245/* Injects the requested processor error or returns info on 1246 * supported injection capabilities for current processor implementation 1247 */ 1248static inline s64 1249ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info, 1250 u64 err_data_buffer, u64 *capabilities, u64 *resources) 1251{ 1252 struct ia64_pal_retval iprv; 1253 PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info, 1254 err_struct_info, err_data_buffer); 1255 if (capabilities) 1256 *capabilities= iprv.v0; 1257 if (resources) 1258 *resources= iprv.v1; 1259 return iprv.status; 1260} 1261 1262static inline s64 1263ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info, 1264 u64 err_data_buffer, u64 *capabilities, u64 *resources) 1265{ 1266 struct ia64_pal_retval iprv; 1267 PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info, 1268 err_struct_info, err_data_buffer); 1269 if (capabilities) 1270 *capabilities= iprv.v0; 1271 if (resources) 1272 *resources= iprv.v1; 1273 return iprv.status; 1274} 1275 1276/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot 1277 * attempt to correct any expected machine checks. 1278 */ 1279static inline s64 1280ia64_pal_mc_expected (u64 expected, u64 *previous) 1281{ 1282 struct ia64_pal_retval iprv; 1283 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0); 1284 if (previous) 1285 *previous = iprv.v0; 1286 return iprv.status; 1287} 1288 1289typedef union pal_hw_tracking_u { 1290 u64 pht_data; 1291 struct { 1292 u64 itc :4, /* Instruction cache tracking */ 1293 dct :4, /* Date cache tracking */ 1294 itt :4, /* Instruction TLB tracking */ 1295 ddt :4, /* Data TLB tracking */ 1296 reserved:48; 1297 } pal_hw_tracking_s; 1298} pal_hw_tracking_u_t; 1299 1300/* 1301 * Hardware tracking status. 1302 */ 1303static inline s64 1304ia64_pal_mc_hw_tracking (u64 *status) 1305{ 1306 struct ia64_pal_retval iprv; 1307 PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0); 1308 if (status) 1309 *status = iprv.v0; 1310 return iprv.status; 1311} 1312 1313/* Register a platform dependent location with PAL to which it can save 1314 * minimal processor state in the event of a machine check or initialization 1315 * event. 1316 */ 1317static inline s64 1318ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size) 1319{ 1320 struct ia64_pal_retval iprv; 1321 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0); 1322 if (req_size) 1323 *req_size = iprv.v0; 1324 return iprv.status; 1325} 1326 1327/* Restore minimal architectural processor state, set CMC interrupt if necessary 1328 * and resume execution 1329 */ 1330static inline s64 1331ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr) 1332{ 1333 struct ia64_pal_retval iprv; 1334 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0); 1335 return iprv.status; 1336} 1337 1338/* Return the memory attributes implemented by the processor */ 1339static inline s64 1340ia64_pal_mem_attrib (u64 *mem_attrib) 1341{ 1342 struct ia64_pal_retval iprv; 1343 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0); 1344 if (mem_attrib) 1345 *mem_attrib = iprv.v0 & 0xff; 1346 return iprv.status; 1347} 1348 1349/* Return the amount of memory needed for second phase of processor 1350 * self-test and the required alignment of memory. 1351 */ 1352static inline s64 1353ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment) 1354{ 1355 struct ia64_pal_retval iprv; 1356 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0); 1357 if (bytes_needed) 1358 *bytes_needed = iprv.v0; 1359 if (alignment) 1360 *alignment = iprv.v1; 1361 return iprv.status; 1362} 1363 1364typedef union pal_perf_mon_info_u { 1365 u64 ppmi_data; 1366 struct { 1367 u64 generic : 8, 1368 width : 8, 1369 cycles : 8, 1370 retired : 8, 1371 reserved : 32; 1372 } pal_perf_mon_info_s; 1373} pal_perf_mon_info_u_t; 1374 1375/* Return the performance monitor information about what can be counted 1376 * and how to configure the monitors to count the desired events. 1377 */ 1378static inline s64 1379ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info) 1380{ 1381 struct ia64_pal_retval iprv; 1382 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0); 1383 if (pm_info) 1384 pm_info->ppmi_data = iprv.v0; 1385 return iprv.status; 1386} 1387 1388/* Specifies the physical address of the processor interrupt block 1389 * and I/O port space. 1390 */ 1391static inline s64 1392ia64_pal_platform_addr (u64 type, u64 physical_addr) 1393{ 1394 struct ia64_pal_retval iprv; 1395 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0); 1396 return iprv.status; 1397} 1398 1399/* Set the SAL PMI entrypoint in memory */ 1400static inline s64 1401ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr) 1402{ 1403 struct ia64_pal_retval iprv; 1404 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0); 1405 return iprv.status; 1406} 1407 1408struct pal_features_s; 1409/* Provide information about configurable processor features */ 1410static inline s64 1411ia64_pal_proc_get_features (u64 *features_avail, 1412 u64 *features_status, 1413 u64 *features_control, 1414 u64 features_set) 1415{ 1416 struct ia64_pal_retval iprv; 1417 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, features_set, 0); 1418 if (iprv.status == 0) { 1419 *features_avail = iprv.v0; 1420 *features_status = iprv.v1; 1421 *features_control = iprv.v2; 1422 } 1423 return iprv.status; 1424} 1425 1426/* Enable/disable processor dependent features */ 1427static inline s64 1428ia64_pal_proc_set_features (u64 feature_select) 1429{ 1430 struct ia64_pal_retval iprv; 1431 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0); 1432 return iprv.status; 1433} 1434 1435/* 1436 * Put everything in a struct so we avoid the global offset table whenever 1437 * possible. 1438 */ 1439typedef struct ia64_ptce_info_s { 1440 unsigned long base; 1441 u32 count[2]; 1442 u32 stride[2]; 1443} ia64_ptce_info_t; 1444 1445/* Return the information required for the architected loop used to purge 1446 * (initialize) the entire TC 1447 */ 1448static inline s64 1449ia64_get_ptce (ia64_ptce_info_t *ptce) 1450{ 1451 struct ia64_pal_retval iprv; 1452 1453 if (!ptce) 1454 return -1; 1455 1456 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0); 1457 if (iprv.status == 0) { 1458 ptce->base = iprv.v0; 1459 ptce->count[0] = iprv.v1 >> 32; 1460 ptce->count[1] = iprv.v1 & 0xffffffff; 1461 ptce->stride[0] = iprv.v2 >> 32; 1462 ptce->stride[1] = iprv.v2 & 0xffffffff; 1463 } 1464 return iprv.status; 1465} 1466 1467/* Return info about implemented application and control registers. */ 1468static inline s64 1469ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2) 1470{ 1471 struct ia64_pal_retval iprv; 1472 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0); 1473 if (reg_info_1) 1474 *reg_info_1 = iprv.v0; 1475 if (reg_info_2) 1476 *reg_info_2 = iprv.v1; 1477 return iprv.status; 1478} 1479 1480typedef union pal_hints_u { 1481 unsigned long ph_data; 1482 struct { 1483 unsigned long si : 1, 1484 li : 1, 1485 reserved : 62; 1486 } pal_hints_s; 1487} pal_hints_u_t; 1488 1489/* Return information about the register stack and RSE for this processor 1490 * implementation. 1491 */ 1492static inline long ia64_pal_rse_info(unsigned long *num_phys_stacked, 1493 pal_hints_u_t *hints) 1494{ 1495 struct ia64_pal_retval iprv; 1496 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0); 1497 if (num_phys_stacked) 1498 *num_phys_stacked = iprv.v0; 1499 if (hints) 1500 hints->ph_data = iprv.v1; 1501 return iprv.status; 1502} 1503 1504/* 1505 * Set the current hardware resource sharing policy of the processor 1506 */ 1507static inline s64 1508ia64_pal_set_hw_policy (u64 policy) 1509{ 1510 struct ia64_pal_retval iprv; 1511 PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0); 1512 return iprv.status; 1513} 1514 1515/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are 1516 * suspended, but cause cache and TLB coherency to be maintained. 1517 * This is usually called in IA-32 mode. 1518 */ 1519static inline s64 1520ia64_pal_shutdown (void) 1521{ 1522 struct ia64_pal_retval iprv; 1523 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0); 1524 return iprv.status; 1525} 1526 1527/* Perform the second phase of processor self-test. */ 1528static inline s64 1529ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state) 1530{ 1531 struct ia64_pal_retval iprv; 1532 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes); 1533 if (self_test_state) 1534 *self_test_state = iprv.v0; 1535 return iprv.status; 1536} 1537 1538typedef union pal_version_u { 1539 u64 pal_version_val; 1540 struct { 1541 u64 pv_pal_b_rev : 8; 1542 u64 pv_pal_b_model : 8; 1543 u64 pv_reserved1 : 8; 1544 u64 pv_pal_vendor : 8; 1545 u64 pv_pal_a_rev : 8; 1546 u64 pv_pal_a_model : 8; 1547 u64 pv_reserved2 : 16; 1548 } pal_version_s; 1549} pal_version_u_t; 1550 1551 1552/* 1553 * Return PAL version information. While the documentation states that 1554 * PAL_VERSION can be called in either physical or virtual mode, some 1555 * implementations only allow physical calls. We don't call it very often, 1556 * so the overhead isn't worth eliminating. 1557 */ 1558static inline s64 1559ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version) 1560{ 1561 struct ia64_pal_retval iprv; 1562 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0); 1563 if (pal_min_version) 1564 pal_min_version->pal_version_val = iprv.v0; 1565 1566 if (pal_cur_version) 1567 pal_cur_version->pal_version_val = iprv.v1; 1568 1569 return iprv.status; 1570} 1571 1572typedef union pal_tc_info_u { 1573 u64 pti_val; 1574 struct { 1575 u64 num_sets : 8, 1576 associativity : 8, 1577 num_entries : 16, 1578 pf : 1, 1579 unified : 1, 1580 reduce_tr : 1, 1581 reserved : 29; 1582 } pal_tc_info_s; 1583} pal_tc_info_u_t; 1584 1585#define tc_reduce_tr pal_tc_info_s.reduce_tr 1586#define tc_unified pal_tc_info_s.unified 1587#define tc_pf pal_tc_info_s.pf 1588#define tc_num_entries pal_tc_info_s.num_entries 1589#define tc_associativity pal_tc_info_s.associativity 1590#define tc_num_sets pal_tc_info_s.num_sets 1591 1592 1593/* Return information about the virtual memory characteristics of the processor 1594 * implementation. 1595 */ 1596static inline s64 1597ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages) 1598{ 1599 struct ia64_pal_retval iprv; 1600 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0); 1601 if (tc_info) 1602 tc_info->pti_val = iprv.v0; 1603 if (tc_pages) 1604 *tc_pages = iprv.v1; 1605 return iprv.status; 1606} 1607 1608/* Get page size information about the virtual memory characteristics of the processor 1609 * implementation. 1610 */ 1611static inline s64 ia64_pal_vm_page_size(u64 *tr_pages, u64 *vw_pages) 1612{ 1613 struct ia64_pal_retval iprv; 1614 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0); 1615 if (tr_pages) 1616 *tr_pages = iprv.v0; 1617 if (vw_pages) 1618 *vw_pages = iprv.v1; 1619 return iprv.status; 1620} 1621 1622typedef union pal_vm_info_1_u { 1623 u64 pvi1_val; 1624 struct { 1625 u64 vw : 1, 1626 phys_add_size : 7, 1627 key_size : 8, 1628 max_pkr : 8, 1629 hash_tag_id : 8, 1630 max_dtr_entry : 8, 1631 max_itr_entry : 8, 1632 max_unique_tcs : 8, 1633 num_tc_levels : 8; 1634 } pal_vm_info_1_s; 1635} pal_vm_info_1_u_t; 1636 1637#define PAL_MAX_PURGES 0xFFFF /* all ones is means unlimited */ 1638 1639typedef union pal_vm_info_2_u { 1640 u64 pvi2_val; 1641 struct { 1642 u64 impl_va_msb : 8, 1643 rid_size : 8, 1644 max_purges : 16, 1645 reserved : 32; 1646 } pal_vm_info_2_s; 1647} pal_vm_info_2_u_t; 1648 1649/* Get summary information about the virtual memory characteristics of the processor 1650 * implementation. 1651 */ 1652static inline s64 1653ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2) 1654{ 1655 struct ia64_pal_retval iprv; 1656 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0); 1657 if (vm_info_1) 1658 vm_info_1->pvi1_val = iprv.v0; 1659 if (vm_info_2) 1660 vm_info_2->pvi2_val = iprv.v1; 1661 return iprv.status; 1662} 1663 1664typedef union pal_vp_info_u { 1665 u64 pvi_val; 1666 struct { 1667 u64 index: 48, /* virtual feature set info */ 1668 vmm_id: 16; /* feature set id */ 1669 } pal_vp_info_s; 1670} pal_vp_info_u_t; 1671 1672/* 1673 * Returns information about virtual processor features 1674 */ 1675static inline s64 1676ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id) 1677{ 1678 struct ia64_pal_retval iprv; 1679 PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0); 1680 if (vp_info) 1681 *vp_info = iprv.v0; 1682 if (vmm_id) 1683 *vmm_id = iprv.v1; 1684 return iprv.status; 1685} 1686 1687typedef union pal_itr_valid_u { 1688 u64 piv_val; 1689 struct { 1690 u64 access_rights_valid : 1, 1691 priv_level_valid : 1, 1692 dirty_bit_valid : 1, 1693 mem_attr_valid : 1, 1694 reserved : 60; 1695 } pal_tr_valid_s; 1696} pal_tr_valid_u_t; 1697 1698/* Read a translation register */ 1699static inline s64 1700ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid) 1701{ 1702 struct ia64_pal_retval iprv; 1703 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer)); 1704 if (tr_valid) 1705 tr_valid->piv_val = iprv.v0; 1706 return iprv.status; 1707} 1708 1709/* 1710 * PAL_PREFETCH_VISIBILITY transaction types 1711 */ 1712#define PAL_VISIBILITY_VIRTUAL 0 1713#define PAL_VISIBILITY_PHYSICAL 1 1714 1715/* 1716 * PAL_PREFETCH_VISIBILITY return codes 1717 */ 1718#define PAL_VISIBILITY_OK 1 1719#define PAL_VISIBILITY_OK_REMOTE_NEEDED 0 1720#define PAL_VISIBILITY_INVAL_ARG -2 1721#define PAL_VISIBILITY_ERROR -3 1722 1723static inline s64 1724ia64_pal_prefetch_visibility (s64 trans_type) 1725{ 1726 struct ia64_pal_retval iprv; 1727 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0); 1728 return iprv.status; 1729} 1730 1731/* data structure for getting information on logical to physical mappings */ 1732typedef union pal_log_overview_u { 1733 struct { 1734 u64 num_log :16, /* Total number of logical 1735 * processors on this die 1736 */ 1737 tpc :8, /* Threads per core */ 1738 reserved3 :8, /* Reserved */ 1739 cpp :8, /* Cores per processor */ 1740 reserved2 :8, /* Reserved */ 1741 ppid :8, /* Physical processor ID */ 1742 reserved1 :8; /* Reserved */ 1743 } overview_bits; 1744 u64 overview_data; 1745} pal_log_overview_t; 1746 1747typedef union pal_proc_n_log_info1_u{ 1748 struct { 1749 u64 tid :16, /* Thread id */ 1750 reserved2 :16, /* Reserved */ 1751 cid :16, /* Core id */ 1752 reserved1 :16; /* Reserved */ 1753 } ppli1_bits; 1754 u64 ppli1_data; 1755} pal_proc_n_log_info1_t; 1756 1757typedef union pal_proc_n_log_info2_u { 1758 struct { 1759 u64 la :16, /* Logical address */ 1760 reserved :48; /* Reserved */ 1761 } ppli2_bits; 1762 u64 ppli2_data; 1763} pal_proc_n_log_info2_t; 1764 1765typedef struct pal_logical_to_physical_s 1766{ 1767 pal_log_overview_t overview; 1768 pal_proc_n_log_info1_t ppli1; 1769 pal_proc_n_log_info2_t ppli2; 1770} pal_logical_to_physical_t; 1771 1772#define overview_num_log overview.overview_bits.num_log 1773#define overview_tpc overview.overview_bits.tpc 1774#define overview_cpp overview.overview_bits.cpp 1775#define overview_ppid overview.overview_bits.ppid 1776#define log1_tid ppli1.ppli1_bits.tid 1777#define log1_cid ppli1.ppli1_bits.cid 1778#define log2_la ppli2.ppli2_bits.la 1779 1780/* Get information on logical to physical processor mappings. */ 1781static inline s64 1782ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping) 1783{ 1784 struct ia64_pal_retval iprv; 1785 1786 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0); 1787 1788 if (iprv.status == PAL_STATUS_SUCCESS) 1789 { 1790 mapping->overview.overview_data = iprv.v0; 1791 mapping->ppli1.ppli1_data = iprv.v1; 1792 mapping->ppli2.ppli2_data = iprv.v2; 1793 } 1794 1795 return iprv.status; 1796} 1797 1798typedef struct pal_cache_shared_info_s 1799{ 1800 u64 num_shared; 1801 pal_proc_n_log_info1_t ppli1; 1802 pal_proc_n_log_info2_t ppli2; 1803} pal_cache_shared_info_t; 1804 1805/* Get information on logical to physical processor mappings. */ 1806static inline s64 1807ia64_pal_cache_shared_info(u64 level, 1808 u64 type, 1809 u64 proc_number, 1810 pal_cache_shared_info_t *info) 1811{ 1812 struct ia64_pal_retval iprv; 1813 1814 PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number); 1815 1816 if (iprv.status == PAL_STATUS_SUCCESS) { 1817 info->num_shared = iprv.v0; 1818 info->ppli1.ppli1_data = iprv.v1; 1819 info->ppli2.ppli2_data = iprv.v2; 1820 } 1821 1822 return iprv.status; 1823} 1824#endif /* __ASSEMBLY__ */ 1825 1826#endif /* _ASM_IA64_PAL_H */ 1827