1/* SPDX-License-Identifier: GPL-2.0 */
2// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
3
4#ifndef __ASM_CSKY_ENTRY_H
5#define __ASM_CSKY_ENTRY_H
6
7#include <asm/setup.h>
8#include <abi/regdef.h>
9
10#define LSAVE_PC	8
11#define LSAVE_PSR	12
12#define LSAVE_A0	24
13#define LSAVE_A1	28
14#define LSAVE_A2	32
15#define LSAVE_A3	36
16#define LSAVE_A4	40
17#define LSAVE_A5	44
18
19#define KSPTOUSP
20#define USPTOKSP
21
22#define usp cr<14, 1>
23
24.macro SAVE_ALL epc_inc
25	subi    sp, 152
26	stw	tls, (sp, 0)
27	stw	lr, (sp, 4)
28
29	mfcr	lr, epc
30	movi	tls, \epc_inc
31	add	lr, tls
32	stw	lr, (sp, 8)
33
34	mfcr	lr, epsr
35	stw	lr, (sp, 12)
36	btsti   lr, 31
37	bf      1f
38	addi    lr, sp, 152
39	br	2f
401:
41	mfcr	lr, usp
422:
43	stw	lr, (sp, 16)
44
45	stw     a0, (sp, 20)
46	stw     a0, (sp, 24)
47	stw     a1, (sp, 28)
48	stw     a2, (sp, 32)
49	stw     a3, (sp, 36)
50
51	addi	sp, 40
52	stm	r4-r13, (sp)
53
54	addi    sp, 40
55	stm     r16-r30, (sp)
56#ifdef CONFIG_CPU_HAS_HILO
57	mfhi	lr
58	stw	lr, (sp, 60)
59	mflo	lr
60	stw	lr, (sp, 64)
61	mfcr	lr, cr14
62	stw	lr, (sp, 68)
63#endif
64	subi	sp, 80
65.endm
66
67.macro	RESTORE_ALL
68	ldw	tls, (sp, 0)
69	ldw	lr, (sp, 4)
70	ldw	a0, (sp, 8)
71	mtcr	a0, epc
72	ldw	a0, (sp, 12)
73	mtcr	a0, epsr
74	btsti   a0, 31
75	ldw	a0, (sp, 16)
76	mtcr	a0, usp
77	mtcr	a0, ss0
78
79#ifdef CONFIG_CPU_HAS_HILO
80	ldw	a0, (sp, 140)
81	mthi	a0
82	ldw	a0, (sp, 144)
83	mtlo	a0
84	ldw	a0, (sp, 148)
85	mtcr	a0, cr14
86#endif
87
88	ldw     a0, (sp, 24)
89	ldw     a1, (sp, 28)
90	ldw     a2, (sp, 32)
91	ldw     a3, (sp, 36)
92
93	addi	sp, 40
94	ldm	r4-r13, (sp)
95	addi    sp, 40
96	ldm     r16-r30, (sp)
97	addi    sp, 72
98	bf	1f
99	mfcr	sp, ss0
1001:
101	rte
102.endm
103
104.macro SAVE_REGS_FTRACE
105	subi    sp, 152
106	stw	tls, (sp, 0)
107	stw	lr, (sp, 4)
108
109	mfcr	lr, psr
110	stw	lr, (sp, 12)
111
112	addi    lr, sp, 152
113	stw	lr, (sp, 16)
114
115	stw     a0, (sp, 20)
116	stw     a0, (sp, 24)
117	stw     a1, (sp, 28)
118	stw     a2, (sp, 32)
119	stw     a3, (sp, 36)
120
121	addi	sp, 40
122	stm	r4-r13, (sp)
123
124	addi    sp, 40
125	stm     r16-r30, (sp)
126#ifdef CONFIG_CPU_HAS_HILO
127	mfhi	lr
128	stw	lr, (sp, 60)
129	mflo	lr
130	stw	lr, (sp, 64)
131	mfcr	lr, cr14
132	stw	lr, (sp, 68)
133#endif
134	subi	sp, 80
135.endm
136
137.macro	RESTORE_REGS_FTRACE
138	ldw	tls, (sp, 0)
139
140#ifdef CONFIG_CPU_HAS_HILO
141	ldw	a0, (sp, 140)
142	mthi	a0
143	ldw	a0, (sp, 144)
144	mtlo	a0
145	ldw	a0, (sp, 148)
146	mtcr	a0, cr14
147#endif
148
149	ldw     a0, (sp, 24)
150	ldw     a1, (sp, 28)
151	ldw     a2, (sp, 32)
152	ldw     a3, (sp, 36)
153
154	addi	sp, 40
155	ldm	r4-r13, (sp)
156	addi    sp, 40
157	ldm     r16-r30, (sp)
158	addi    sp, 72
159.endm
160
161.macro SAVE_SWITCH_STACK
162	subi    sp, 64
163	stm	r4-r11, (sp)
164	stw	lr,  (sp, 32)
165	stw	r16, (sp, 36)
166	stw	r17, (sp, 40)
167	stw	r26, (sp, 44)
168	stw	r27, (sp, 48)
169	stw	r28, (sp, 52)
170	stw	r29, (sp, 56)
171	stw	r30, (sp, 60)
172#ifdef CONFIG_CPU_HAS_HILO
173	subi	sp, 16
174	mfhi	lr
175	stw	lr, (sp, 0)
176	mflo	lr
177	stw	lr, (sp, 4)
178	mfcr	lr, cr14
179	stw	lr, (sp, 8)
180#endif
181.endm
182
183.macro RESTORE_SWITCH_STACK
184#ifdef CONFIG_CPU_HAS_HILO
185	ldw	lr, (sp, 0)
186	mthi	lr
187	ldw	lr, (sp, 4)
188	mtlo	lr
189	ldw	lr, (sp, 8)
190	mtcr	lr, cr14
191	addi	sp, 16
192#endif
193	ldm	r4-r11, (sp)
194	ldw	lr,  (sp, 32)
195	ldw	r16, (sp, 36)
196	ldw	r17, (sp, 40)
197	ldw	r26, (sp, 44)
198	ldw	r27, (sp, 48)
199	ldw	r28, (sp, 52)
200	ldw	r29, (sp, 56)
201	ldw	r30, (sp, 60)
202	addi	sp, 64
203.endm
204
205/* MMU registers operators. */
206.macro RD_MIR rx
207	mfcr	\rx, cr<0, 15>
208.endm
209
210.macro RD_MEH rx
211	mfcr	\rx, cr<4, 15>
212.endm
213
214.macro RD_MCIR rx
215	mfcr	\rx, cr<8, 15>
216.endm
217
218.macro RD_PGDR rx
219	mfcr	\rx, cr<29, 15>
220.endm
221
222.macro RD_PGDR_K rx
223	mfcr	\rx, cr<28, 15>
224.endm
225
226.macro WR_MEH rx
227	mtcr	\rx, cr<4, 15>
228.endm
229
230.macro WR_MCIR rx
231	mtcr	\rx, cr<8, 15>
232.endm
233
234.macro SETUP_MMU
235	/* Init psr and enable ee */
236	lrw	r6, DEFAULT_PSR_VALUE
237	mtcr    r6, psr
238	psrset  ee
239
240	/* Invalid I/Dcache BTB BHT */
241	movi	r6, 7
242	lsli	r6, 16
243	addi	r6, (1<<4) | 3
244	mtcr	r6, cr17
245
246	/* Invalid all TLB */
247	bgeni   r6, 26
248	mtcr	r6, cr<8, 15> /* Set MCIR */
249
250	/* Check MMU on/off */
251	mfcr	r6, cr18
252	btsti	r6, 0
253	bt	1f
254
255	/* MMU off: setup mapping tlb entry */
256	movi	r6, 0
257	mtcr	r6, cr<6, 15> /* Set MPR with 4K page size */
258
259	grs	r6, 1f /* Get current pa by PC */
260	bmaski  r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */
261	andn    r6, r7
262	mtcr	r6, cr<4, 15> /* Set MEH */
263
264	mov	r8, r6
265	movi    r7, 0x00000006
266	or      r8, r7
267	mtcr	r8, cr<2, 15> /* Set MEL0 */
268	movi    r7, 0x00001006
269	or      r8, r7
270	mtcr	r8, cr<3, 15> /* Set MEL1 */
271
272	bgeni   r8, 28
273	mtcr	r8, cr<8, 15> /* Set MCIR to write TLB */
274
275	br	2f
2761:
277	/*
278	 * MMU on: use origin MSA value from bootloader
279	 *
280	 * cr<30/31, 15> MSA register format:
281	 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
282	 *   BA     Reserved  SH  WA  B   SO SEC  C   D   V
283	 */
284	mfcr	r6, cr<30, 15> /* Get MSA0 */
2852:
286	lsri	r6, 29
287	lsli	r6, 29
288	addi	r6, 0x1ce
289	mtcr	r6, cr<30, 15> /* Set MSA0 */
290
291	movi    r6, 0
292	mtcr	r6, cr<31, 15> /* Clr MSA1 */
293
294	/* enable MMU */
295	mfcr    r6, cr18
296	bseti	r6, 0
297	mtcr    r6, cr18
298
299	jmpi	3f /* jump to va */
3003:
301.endm
302#endif /* __ASM_CSKY_ENTRY_H */
303