1/* SPDX-License-Identifier: GPL-2.0 */
2// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
3
4#ifndef __ASM_CSKY_CKMMUV1_H
5#define __ASM_CSKY_CKMMUV1_H
6#include <abi/reg_ops.h>
7
8static inline int read_mmu_index(void)
9{
10	return cprcr("cpcr0");
11}
12
13static inline void write_mmu_index(int value)
14{
15	cpwcr("cpcr0", value);
16}
17
18static inline int read_mmu_entrylo0(void)
19{
20	return cprcr("cpcr2") << 6;
21}
22
23static inline int read_mmu_entrylo1(void)
24{
25	return cprcr("cpcr3") << 6;
26}
27
28static inline void write_mmu_pagemask(int value)
29{
30	cpwcr("cpcr6", value);
31}
32
33static inline int read_mmu_entryhi(void)
34{
35	return cprcr("cpcr4");
36}
37
38static inline void write_mmu_entryhi(int value)
39{
40	cpwcr("cpcr4", value);
41}
42
43static inline unsigned long read_mmu_msa0(void)
44{
45	return cprcr("cpcr30");
46}
47
48static inline void write_mmu_msa0(unsigned long value)
49{
50	cpwcr("cpcr30", value);
51}
52
53static inline unsigned long read_mmu_msa1(void)
54{
55	return cprcr("cpcr31");
56}
57
58static inline void write_mmu_msa1(unsigned long value)
59{
60	cpwcr("cpcr31", value);
61}
62
63/*
64 * TLB operations.
65 */
66static inline void tlb_probe(void)
67{
68	cpwcr("cpcr8", 0x80000000);
69}
70
71static inline void tlb_read(void)
72{
73	cpwcr("cpcr8", 0x40000000);
74}
75
76static inline void tlb_invalid_all(void)
77{
78	cpwcr("cpcr8", 0x04000000);
79}
80
81
82static inline void local_tlb_invalid_all(void)
83{
84	tlb_invalid_all();
85}
86
87static inline void tlb_invalid_indexed(void)
88{
89	cpwcr("cpcr8", 0x02000000);
90}
91
92static inline void setup_pgd(unsigned long pgd, bool kernel)
93{
94	cpwcr("cpcr29", pgd | BIT(0));
95}
96
97static inline unsigned long get_pgd(void)
98{
99	return cprcr("cpcr29") & ~BIT(0);
100}
101#endif /* __ASM_CSKY_CKMMUV1_H */
102