1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *  Port on Texas Instruments TMS320C6x architecture
4 *
5 *  Copyright (C) 2004, 2009, 2010, 2011 Texas Instruments Incorporated
6 *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
7 */
8#ifndef _ASM_C6X_SPECIAL_INSNS_H
9#define _ASM_C6X_SPECIAL_INSNS_H
10
11
12#define get_creg(reg) \
13	({ unsigned int __x; \
14	   asm volatile ("mvc .s2 " #reg ",%0\n" : "=b"(__x)); __x; })
15
16#define set_creg(reg, v) \
17	do { unsigned int __x = (unsigned int)(v); \
18		asm volatile ("mvc .s2 %0," #reg "\n" : : "b"(__x)); \
19	} while (0)
20
21#define or_creg(reg, n) \
22	do { unsigned __x, __n = (unsigned)(n);		  \
23		asm volatile ("mvc .s2 " #reg ",%0\n"	  \
24			      "or  .l2 %1,%0,%0\n"	  \
25			      "mvc .s2 %0," #reg "\n"	  \
26			      "nop\n"			  \
27			      : "=&b"(__x) : "b"(__n));	  \
28	} while (0)
29
30#define and_creg(reg, n) \
31	do { unsigned __x, __n = (unsigned)(n);		  \
32		asm volatile ("mvc .s2 " #reg ",%0\n"	  \
33			      "and .l2 %1,%0,%0\n"	  \
34			      "mvc .s2 %0," #reg "\n"	  \
35			      "nop\n"    \
36			      : "=&b"(__x) : "b"(__n));	  \
37	} while (0)
38
39#define get_coreid() (get_creg(DNUM) & 0xff)
40
41/* Set/get IST */
42#define set_ist(x)	set_creg(ISTP, x)
43#define get_ist()       get_creg(ISTP)
44
45/*
46 * Exception management
47 */
48#define disable_exception()
49#define get_except_type()        get_creg(EFR)
50#define ack_exception(type)      set_creg(ECR, 1 << (type))
51#define get_iexcept()            get_creg(IERR)
52#define set_iexcept(mask)        set_creg(IERR, (mask))
53
54#define _extu(x, s, e)							\
55	({      unsigned int __x;					\
56		asm volatile ("extu .S2 %3,%1,%2,%0\n" :		\
57			      "=b"(__x) : "n"(s), "n"(e), "b"(x));	\
58	       __x; })
59
60#endif /* _ASM_C6X_SPECIAL_INSNS_H */
61