1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#include <hyp/switch.h>
8
9#include <linux/arm-smccc.h>
10#include <linux/kvm_host.h>
11#include <linux/types.h>
12#include <linux/jump_label.h>
13#include <linux/percpu.h>
14#include <uapi/linux/psci.h>
15
16#include <kvm/arm_psci.h>
17
18#include <asm/barrier.h>
19#include <asm/cpufeature.h>
20#include <asm/kprobes.h>
21#include <asm/kvm_asm.h>
22#include <asm/kvm_emulate.h>
23#include <asm/kvm_hyp.h>
24#include <asm/kvm_mmu.h>
25#include <asm/fpsimd.h>
26#include <asm/debug-monitors.h>
27#include <asm/processor.h>
28#include <asm/thread_info.h>
29#include <asm/vectors.h>
30
31const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n";
32
33/* VHE specific context */
34DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
35DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
36DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
37
38static void __activate_traps(struct kvm_vcpu *vcpu)
39{
40	u64 val;
41
42	___activate_traps(vcpu);
43
44	val = read_sysreg(cpacr_el1);
45	val |= CPACR_EL1_TTA;
46	val &= ~CPACR_EL1_ZEN;
47
48	/*
49	 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
50	 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
51	 * except for some missing controls, such as TAM.
52	 * In this case, CPTR_EL2.TAM has the same position with or without
53	 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
54	 * shift value for trapping the AMU accesses.
55	 */
56
57	val |= CPTR_EL2_TAM;
58
59	if (update_fp_enabled(vcpu)) {
60		if (vcpu_has_sve(vcpu))
61			val |= CPACR_EL1_ZEN;
62	} else {
63		val &= ~CPACR_EL1_FPEN;
64		__activate_traps_fpsimd32(vcpu);
65	}
66
67	write_sysreg(val, cpacr_el1);
68
69	write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1);
70}
71NOKPROBE_SYMBOL(__activate_traps);
72
73static void __deactivate_traps(struct kvm_vcpu *vcpu)
74{
75	const char *host_vectors = vectors;
76
77	___deactivate_traps(vcpu);
78
79	write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
80
81	/*
82	 * ARM errata 1165522 and 1530923 require the actual execution of the
83	 * above before we can switch to the EL2/EL0 translation regime used by
84	 * the host.
85	 */
86	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
87
88	write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);
89
90	if (!arm64_kernel_unmapped_at_el0())
91		host_vectors = __this_cpu_read(this_cpu_vector);
92	write_sysreg(host_vectors, vbar_el1);
93}
94NOKPROBE_SYMBOL(__deactivate_traps);
95
96void activate_traps_vhe_load(struct kvm_vcpu *vcpu)
97{
98	__activate_traps_common(vcpu);
99}
100
101void deactivate_traps_vhe_put(void)
102{
103	u64 mdcr_el2 = read_sysreg(mdcr_el2);
104
105	mdcr_el2 &= MDCR_EL2_HPMN_MASK |
106		    MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT |
107		    MDCR_EL2_TPMS;
108
109	write_sysreg(mdcr_el2, mdcr_el2);
110
111	__deactivate_traps_common();
112}
113
114/* Switch to the guest for VHE systems running in EL2 */
115static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
116{
117	struct kvm_cpu_context *host_ctxt;
118	struct kvm_cpu_context *guest_ctxt;
119	u64 exit_code;
120
121	host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
122	host_ctxt->__hyp_running_vcpu = vcpu;
123	guest_ctxt = &vcpu->arch.ctxt;
124
125	sysreg_save_host_state_vhe(host_ctxt);
126
127	/*
128	 * ARM erratum 1165522 requires us to configure both stage 1 and
129	 * stage 2 translation for the guest context before we clear
130	 * HCR_EL2.TGE.
131	 *
132	 * We have already configured the guest's stage 1 translation in
133	 * kvm_vcpu_load_sysregs_vhe above.  We must now call
134	 * __load_guest_stage2 before __activate_traps, because
135	 * __load_guest_stage2 configures stage 2 translation, and
136	 * __activate_traps clear HCR_EL2.TGE (among other things).
137	 */
138	__load_guest_stage2(vcpu->arch.hw_mmu);
139	__activate_traps(vcpu);
140
141	sysreg_restore_guest_state_vhe(guest_ctxt);
142	__debug_switch_to_guest(vcpu);
143
144	do {
145		/* Jump in the fire! */
146		exit_code = __guest_enter(vcpu);
147
148		/* And we're baaack! */
149	} while (fixup_guest_exit(vcpu, &exit_code));
150
151	sysreg_save_guest_state_vhe(guest_ctxt);
152
153	__deactivate_traps(vcpu);
154
155	sysreg_restore_host_state_vhe(host_ctxt);
156
157	if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED)
158		__fpsimd_save_fpexc32(vcpu);
159
160	__debug_switch_to_host(vcpu);
161
162	return exit_code;
163}
164NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
165
166int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
167{
168	int ret;
169
170	local_daif_mask();
171
172	/*
173	 * Having IRQs masked via PMR when entering the guest means the GIC
174	 * will not signal the CPU of interrupts of lower priority, and the
175	 * only way to get out will be via guest exceptions.
176	 * Naturally, we want to avoid this.
177	 *
178	 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
179	 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
180	 */
181	pmr_sync();
182
183	ret = __kvm_vcpu_run_vhe(vcpu);
184
185	/*
186	 * local_daif_restore() takes care to properly restore PSTATE.DAIF
187	 * and the GIC PMR if the host is using IRQ priorities.
188	 */
189	local_daif_restore(DAIF_PROCCTX_NOIRQ);
190
191	/*
192	 * When we exit from the guest we change a number of CPU configuration
193	 * parameters, such as traps.  Make sure these changes take effect
194	 * before running the host or additional guests.
195	 */
196	isb();
197
198	return ret;
199}
200
201static void __hyp_call_panic(u64 spsr, u64 elr, u64 par)
202{
203	struct kvm_cpu_context *host_ctxt;
204	struct kvm_vcpu *vcpu;
205
206	host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
207	vcpu = host_ctxt->__hyp_running_vcpu;
208
209	__deactivate_traps(vcpu);
210	sysreg_restore_host_state_vhe(host_ctxt);
211
212	panic(__hyp_panic_string,
213	      spsr, elr,
214	      read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR),
215	      read_sysreg(hpfar_el2), par, vcpu);
216}
217NOKPROBE_SYMBOL(__hyp_call_panic);
218
219void __noreturn hyp_panic(void)
220{
221	u64 spsr = read_sysreg_el2(SYS_SPSR);
222	u64 elr = read_sysreg_el2(SYS_ELR);
223	u64 par = read_sysreg_par();
224
225	__hyp_call_panic(spsr, elr, par);
226	unreachable();
227}
228
229asmlinkage void kvm_unexpected_el2_exception(void)
230{
231	__kvm_unexpected_el2_exception();
232}
233