1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9#ifndef __ASM_SYSREG_H 10#define __ASM_SYSREG_H 11 12#include <linux/bits.h> 13#include <linux/stringify.h> 14 15/* 16 * ARMv8 ARM reserves the following encoding for system registers: 17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 18 * C5.2, version:ARM DDI 0487A.f) 19 * [20-19] : Op0 20 * [18-16] : Op1 21 * [15-12] : CRn 22 * [11-8] : CRm 23 * [7-5] : Op2 24 */ 25#define Op0_shift 19 26#define Op0_mask 0x3 27#define Op1_shift 16 28#define Op1_mask 0x7 29#define CRn_shift 12 30#define CRn_mask 0xf 31#define CRm_shift 8 32#define CRm_mask 0xf 33#define Op2_shift 5 34#define Op2_mask 0x7 35 36#define sys_reg(op0, op1, crn, crm, op2) \ 37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 39 ((op2) << Op2_shift)) 40 41#define sys_insn sys_reg 42 43#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 44#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 45#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 46#define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 47#define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 48 49#ifndef CONFIG_BROKEN_GAS_INST 50 51#ifdef __ASSEMBLY__ 52// The space separator is omitted so that __emit_inst(x) can be parsed as 53// either an assembler directive or an assembler macro argument. 54#define __emit_inst(x) .inst(x) 55#else 56#define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 57#endif 58 59#else /* CONFIG_BROKEN_GAS_INST */ 60 61#ifndef CONFIG_CPU_BIG_ENDIAN 62#define __INSTR_BSWAP(x) (x) 63#else /* CONFIG_CPU_BIG_ENDIAN */ 64#define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 65 (((x) << 8) & 0x00ff0000) | \ 66 (((x) >> 8) & 0x0000ff00) | \ 67 (((x) >> 24) & 0x000000ff)) 68#endif /* CONFIG_CPU_BIG_ENDIAN */ 69 70#ifdef __ASSEMBLY__ 71#define __emit_inst(x) .long __INSTR_BSWAP(x) 72#else /* __ASSEMBLY__ */ 73#define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 74#endif /* __ASSEMBLY__ */ 75 76#endif /* CONFIG_BROKEN_GAS_INST */ 77 78/* 79 * Instructions for modifying PSTATE fields. 80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 81 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 82 * for accessing PSTATE fields have the following encoding: 83 * Op0 = 0, CRn = 4 84 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 85 * CRm = Imm4 for the instruction. 86 * Rt = 0x1f 87 */ 88#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 89#define PSTATE_Imm_shift CRm_shift 90 91#define PSTATE_PAN pstate_field(0, 4) 92#define PSTATE_UAO pstate_field(0, 3) 93#define PSTATE_SSBS pstate_field(3, 1) 94#define PSTATE_TCO pstate_field(3, 4) 95 96#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 97#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 98#define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 99#define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift)) 100 101#define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 102 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 103 104#define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 105 106#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 107#define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) 108#define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) 109#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 110#define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) 111#define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) 112#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 113#define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) 114#define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) 115 116/* 117 * System registers, organised loosely by encoding but grouped together 118 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 119 */ 120#define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 121#define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 122#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 123#define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 124#define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 125#define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 126#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 127#define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 128#define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 129#define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 130#define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 131#define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 132#define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 133#define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 134#define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 135#define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 136#define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 137#define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 138#define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 139#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 140#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 141#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 142 143#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 144#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 145#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 146 147#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 148#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 149#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) 150#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 151#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) 152#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 153#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 154#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 155#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 156#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 157#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 158#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) 159 160#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 161#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 162#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 163#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 164#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 165#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 166#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) 167 168#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 169#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 170#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 171 172#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 173#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 174#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 175 176#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 177#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 178 179#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 180#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 181 182#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 183#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 184#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) 185 186#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 187#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 188#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 189 190#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 191#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 192#define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 193#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 194#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 195 196#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 197 198#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 199#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 200#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 201 202#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 203#define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 204#define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 205#define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 206 207#define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 208#define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 209#define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 210#define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 211 212#define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 213#define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 214 215#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 216#define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 217 218#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 219 220#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 221#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 222#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 223 224#define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 225#define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 226#define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 227#define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 228#define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 229#define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 230#define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 231#define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 232#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 233#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) 234 235#define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 236#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 237 238#define SYS_PAR_EL1_F BIT(0) 239#define SYS_PAR_EL1_FST GENMASK(6, 1) 240 241/*** Statistical Profiling Extension ***/ 242/* ID registers */ 243#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 244#define SYS_PMSIDR_EL1_FE_SHIFT 0 245#define SYS_PMSIDR_EL1_FT_SHIFT 1 246#define SYS_PMSIDR_EL1_FL_SHIFT 2 247#define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 248#define SYS_PMSIDR_EL1_LDS_SHIFT 4 249#define SYS_PMSIDR_EL1_ERND_SHIFT 5 250#define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 251#define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 252#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 253#define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 254#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 255#define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 256 257#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 258#define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 259#define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 260#define SYS_PMBIDR_EL1_P_SHIFT 4 261#define SYS_PMBIDR_EL1_F_SHIFT 5 262 263/* Sampling controls */ 264#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 265#define SYS_PMSCR_EL1_E0SPE_SHIFT 0 266#define SYS_PMSCR_EL1_E1SPE_SHIFT 1 267#define SYS_PMSCR_EL1_CX_SHIFT 3 268#define SYS_PMSCR_EL1_PA_SHIFT 4 269#define SYS_PMSCR_EL1_TS_SHIFT 5 270#define SYS_PMSCR_EL1_PCT_SHIFT 6 271 272#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 273#define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 274#define SYS_PMSCR_EL2_E2SPE_SHIFT 1 275#define SYS_PMSCR_EL2_CX_SHIFT 3 276#define SYS_PMSCR_EL2_PA_SHIFT 4 277#define SYS_PMSCR_EL2_TS_SHIFT 5 278#define SYS_PMSCR_EL2_PCT_SHIFT 6 279 280#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 281 282#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 283#define SYS_PMSIRR_EL1_RND_SHIFT 0 284#define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 285#define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 286 287/* Filtering controls */ 288#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 289#define SYS_PMSFCR_EL1_FE_SHIFT 0 290#define SYS_PMSFCR_EL1_FT_SHIFT 1 291#define SYS_PMSFCR_EL1_FL_SHIFT 2 292#define SYS_PMSFCR_EL1_B_SHIFT 16 293#define SYS_PMSFCR_EL1_LD_SHIFT 17 294#define SYS_PMSFCR_EL1_ST_SHIFT 18 295 296#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 297#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL 298 299#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 300#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 301 302/* Buffer controls */ 303#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 304#define SYS_PMBLIMITR_EL1_E_SHIFT 0 305#define SYS_PMBLIMITR_EL1_FM_SHIFT 1 306#define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 307#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 308 309#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 310 311/* Buffer error reporting */ 312#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 313#define SYS_PMBSR_EL1_COLL_SHIFT 16 314#define SYS_PMBSR_EL1_S_SHIFT 17 315#define SYS_PMBSR_EL1_EA_SHIFT 18 316#define SYS_PMBSR_EL1_DL_SHIFT 19 317#define SYS_PMBSR_EL1_EC_SHIFT 26 318#define SYS_PMBSR_EL1_EC_MASK 0x3fUL 319 320#define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 321#define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 322#define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 323 324#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 325#define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 326 327#define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 328#define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 329 330#define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 331 332/*** End of Statistical Profiling Extension ***/ 333 334#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 335#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 336 337#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) 338 339#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 340#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 341 342#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 343#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 344#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 345#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 346#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 347 348#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 349#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 350 351#define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 352#define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 353#define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 354#define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 355#define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 356#define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 357#define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 358#define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 359#define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 360#define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 361#define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 362#define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 363#define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 364#define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 365#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 366#define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 367#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 368#define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 369#define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 370#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 371#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 372#define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 373#define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 374#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 375#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 376#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 377#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 378 379#define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 380#define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 381 382#define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7) 383 384#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 385 386#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 387#define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 388#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4) 389#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 390 391#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 392 393#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 394#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 395 396#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 397#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 398 399#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 400#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 401#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 402#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 403#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 404#define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 405#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 406#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 407#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 408#define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 409#define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 410#define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 411#define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 412 413#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 414#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 415 416#define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) 417 418/* Definitions for system register interface to AMU for ARMv8.4 onwards */ 419#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 420#define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 421#define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 422#define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 423#define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 424#define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 425#define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 426#define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 427#define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 428 429/* 430 * Group 0 of activity monitors (architected): 431 * op0 op1 CRn CRm op2 432 * Counter: 11 011 1101 010:n<3> n<2:0> 433 * Type: 11 011 1101 011:n<3> n<2:0> 434 * n: 0-15 435 * 436 * Group 1 of activity monitors (auxiliary): 437 * op0 op1 CRn CRm op2 438 * Counter: 11 011 1101 110:n<3> n<2:0> 439 * Type: 11 011 1101 111:n<3> n<2:0> 440 * n: 0-15 441 */ 442 443#define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 444#define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 445#define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 446#define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 447 448/* AMU v1: Fixed (architecturally defined) activity monitors */ 449#define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 450#define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 451#define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 452#define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 453 454#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 455 456#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 457#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 458#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 459 460#define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 461#define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 462 463#define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 464#define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 465#define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 466 467#define __PMEV_op2(n) ((n) & 0x7) 468#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 469#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 470#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 471#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 472 473#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 474 475#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 476#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 477#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 478#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 479#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 480#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 481#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 482#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 483#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) 484#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 485 486#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 487#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 488#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 489#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 490#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 491#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 492 493#define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 494#define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 495#define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 496#define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 497#define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 498 499#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 500#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 501#define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 502#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 503#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 504#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 505#define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 506#define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 507 508#define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 509#define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 510#define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 511#define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 512#define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 513#define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 514#define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 515#define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 516#define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 517 518#define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 519#define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 520#define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 521#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 522#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 523#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 524#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 525#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 526#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 527 528/* VHE encodings for architectural EL0/1 system registers */ 529#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 530#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) 531#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) 532#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 533#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 534#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 535#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 536#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 537#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 538#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 539#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 540#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) 541#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) 542#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 543#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 544#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 545#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) 546#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 547#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 548#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 549#define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 550#define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 551#define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 552#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 553 554/* Common SCTLR_ELx flags. */ 555#define SCTLR_ELx_DSSBS (BIT(44)) 556#define SCTLR_ELx_ATA (BIT(43)) 557 558#define SCTLR_ELx_TCF_SHIFT 40 559#define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT) 560#define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT) 561#define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT) 562#define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT) 563 564#define SCTLR_ELx_ITFSB (BIT(37)) 565#define SCTLR_ELx_ENIA (BIT(31)) 566#define SCTLR_ELx_ENIB (BIT(30)) 567#define SCTLR_ELx_ENDA (BIT(27)) 568#define SCTLR_ELx_EE (BIT(25)) 569#define SCTLR_ELx_IESB (BIT(21)) 570#define SCTLR_ELx_WXN (BIT(19)) 571#define SCTLR_ELx_ENDB (BIT(13)) 572#define SCTLR_ELx_I (BIT(12)) 573#define SCTLR_ELx_SA (BIT(3)) 574#define SCTLR_ELx_C (BIT(2)) 575#define SCTLR_ELx_A (BIT(1)) 576#define SCTLR_ELx_M (BIT(0)) 577 578#define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 579 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) 580 581/* SCTLR_EL2 specific flags. */ 582#define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 583 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 584 (BIT(29))) 585 586#ifdef CONFIG_CPU_BIG_ENDIAN 587#define ENDIAN_SET_EL2 SCTLR_ELx_EE 588#else 589#define ENDIAN_SET_EL2 0 590#endif 591 592/* SCTLR_EL1 specific flags. */ 593#define SCTLR_EL1_ATA0 (BIT(42)) 594 595#define SCTLR_EL1_TCF0_SHIFT 38 596#define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT) 597#define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT) 598#define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT) 599#define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT) 600 601#define SCTLR_EL1_BT1 (BIT(36)) 602#define SCTLR_EL1_BT0 (BIT(35)) 603#define SCTLR_EL1_UCI (BIT(26)) 604#define SCTLR_EL1_E0E (BIT(24)) 605#define SCTLR_EL1_SPAN (BIT(23)) 606#define SCTLR_EL1_NTWE (BIT(18)) 607#define SCTLR_EL1_NTWI (BIT(16)) 608#define SCTLR_EL1_UCT (BIT(15)) 609#define SCTLR_EL1_DZE (BIT(14)) 610#define SCTLR_EL1_UMA (BIT(9)) 611#define SCTLR_EL1_SED (BIT(8)) 612#define SCTLR_EL1_ITD (BIT(7)) 613#define SCTLR_EL1_CP15BEN (BIT(5)) 614#define SCTLR_EL1_SA0 (BIT(4)) 615 616#define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ 617 (BIT(29))) 618 619#ifdef CONFIG_CPU_BIG_ENDIAN 620#define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 621#else 622#define ENDIAN_SET_EL1 0 623#endif 624 625#define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\ 626 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\ 627 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\ 628 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\ 629 SCTLR_ELx_ITFSB| SCTLR_ELx_ATA | SCTLR_EL1_ATA0 |\ 630 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1) 631 632/* MAIR_ELx memory attributes (used by Linux) */ 633#define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 634#define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 635#define MAIR_ATTR_DEVICE_GRE UL(0x0c) 636#define MAIR_ATTR_NORMAL_NC UL(0x44) 637#define MAIR_ATTR_NORMAL_WT UL(0xbb) 638#define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) 639#define MAIR_ATTR_NORMAL UL(0xff) 640#define MAIR_ATTR_MASK UL(0xff) 641 642/* Position the attr at the correct index */ 643#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 644 645/* id_aa64isar0 */ 646#define ID_AA64ISAR0_RNDR_SHIFT 60 647#define ID_AA64ISAR0_TLB_SHIFT 56 648#define ID_AA64ISAR0_TS_SHIFT 52 649#define ID_AA64ISAR0_FHM_SHIFT 48 650#define ID_AA64ISAR0_DP_SHIFT 44 651#define ID_AA64ISAR0_SM4_SHIFT 40 652#define ID_AA64ISAR0_SM3_SHIFT 36 653#define ID_AA64ISAR0_SHA3_SHIFT 32 654#define ID_AA64ISAR0_RDM_SHIFT 28 655#define ID_AA64ISAR0_ATOMICS_SHIFT 20 656#define ID_AA64ISAR0_CRC32_SHIFT 16 657#define ID_AA64ISAR0_SHA2_SHIFT 12 658#define ID_AA64ISAR0_SHA1_SHIFT 8 659#define ID_AA64ISAR0_AES_SHIFT 4 660 661#define ID_AA64ISAR0_TLB_RANGE_NI 0x0 662#define ID_AA64ISAR0_TLB_RANGE 0x2 663 664/* id_aa64isar1 */ 665#define ID_AA64ISAR1_I8MM_SHIFT 52 666#define ID_AA64ISAR1_DGH_SHIFT 48 667#define ID_AA64ISAR1_BF16_SHIFT 44 668#define ID_AA64ISAR1_SPECRES_SHIFT 40 669#define ID_AA64ISAR1_SB_SHIFT 36 670#define ID_AA64ISAR1_FRINTTS_SHIFT 32 671#define ID_AA64ISAR1_GPI_SHIFT 28 672#define ID_AA64ISAR1_GPA_SHIFT 24 673#define ID_AA64ISAR1_LRCPC_SHIFT 20 674#define ID_AA64ISAR1_FCMA_SHIFT 16 675#define ID_AA64ISAR1_JSCVT_SHIFT 12 676#define ID_AA64ISAR1_API_SHIFT 8 677#define ID_AA64ISAR1_APA_SHIFT 4 678#define ID_AA64ISAR1_DPB_SHIFT 0 679 680#define ID_AA64ISAR1_APA_NI 0x0 681#define ID_AA64ISAR1_APA_ARCHITECTED 0x1 682#define ID_AA64ISAR1_APA_ARCH_EPAC 0x2 683#define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3 684#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4 685#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5 686#define ID_AA64ISAR1_API_NI 0x0 687#define ID_AA64ISAR1_API_IMP_DEF 0x1 688#define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2 689#define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3 690#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4 691#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5 692#define ID_AA64ISAR1_GPA_NI 0x0 693#define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 694#define ID_AA64ISAR1_GPI_NI 0x0 695#define ID_AA64ISAR1_GPI_IMP_DEF 0x1 696#define ID_AA64ISAR2_CLEARBHB_SHIFT 28 697 698/* id_aa64isar2 */ 699#define ID_AA64ISAR2_RPRES_SHIFT 4 700#define ID_AA64ISAR2_WFXT_SHIFT 0 701 702#define ID_AA64ISAR2_RPRES_8BIT 0x0 703#define ID_AA64ISAR2_RPRES_12BIT 0x1 704/* 705 * Value 0x1 has been removed from the architecture, and is 706 * reserved, but has not yet been removed from the ARM ARM 707 * as of ARM DDI 0487G.b. 708 */ 709#define ID_AA64ISAR2_WFXT_NI 0x0 710#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 711 712/* id_aa64pfr0 */ 713#define ID_AA64PFR0_CSV3_SHIFT 60 714#define ID_AA64PFR0_CSV2_SHIFT 56 715#define ID_AA64PFR0_DIT_SHIFT 48 716#define ID_AA64PFR0_AMU_SHIFT 44 717#define ID_AA64PFR0_MPAM_SHIFT 40 718#define ID_AA64PFR0_SEL2_SHIFT 36 719#define ID_AA64PFR0_SVE_SHIFT 32 720#define ID_AA64PFR0_RAS_SHIFT 28 721#define ID_AA64PFR0_GIC_SHIFT 24 722#define ID_AA64PFR0_ASIMD_SHIFT 20 723#define ID_AA64PFR0_FP_SHIFT 16 724#define ID_AA64PFR0_EL3_SHIFT 12 725#define ID_AA64PFR0_EL2_SHIFT 8 726#define ID_AA64PFR0_EL1_SHIFT 4 727#define ID_AA64PFR0_EL0_SHIFT 0 728 729#define ID_AA64PFR0_AMU 0x1 730#define ID_AA64PFR0_SVE 0x1 731#define ID_AA64PFR0_RAS_V1 0x1 732#define ID_AA64PFR0_FP_NI 0xf 733#define ID_AA64PFR0_FP_SUPPORTED 0x0 734#define ID_AA64PFR0_ASIMD_NI 0xf 735#define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 736#define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 737#define ID_AA64PFR0_EL1_32BIT_64BIT 0x2 738#define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 739#define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 740 741/* id_aa64pfr1 */ 742#define ID_AA64PFR1_MPAMFRAC_SHIFT 16 743#define ID_AA64PFR1_RASFRAC_SHIFT 12 744#define ID_AA64PFR1_MTE_SHIFT 8 745#define ID_AA64PFR1_SSBS_SHIFT 4 746#define ID_AA64PFR1_BT_SHIFT 0 747 748#define ID_AA64PFR1_SSBS_PSTATE_NI 0 749#define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 750#define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 751#define ID_AA64PFR1_BT_BTI 0x1 752 753#define ID_AA64PFR1_MTE_NI 0x0 754#define ID_AA64PFR1_MTE_EL0 0x1 755#define ID_AA64PFR1_MTE 0x2 756 757/* id_aa64zfr0 */ 758#define ID_AA64ZFR0_F64MM_SHIFT 56 759#define ID_AA64ZFR0_F32MM_SHIFT 52 760#define ID_AA64ZFR0_I8MM_SHIFT 44 761#define ID_AA64ZFR0_SM4_SHIFT 40 762#define ID_AA64ZFR0_SHA3_SHIFT 32 763#define ID_AA64ZFR0_BF16_SHIFT 20 764#define ID_AA64ZFR0_BITPERM_SHIFT 16 765#define ID_AA64ZFR0_AES_SHIFT 4 766#define ID_AA64ZFR0_SVEVER_SHIFT 0 767 768#define ID_AA64ZFR0_F64MM 0x1 769#define ID_AA64ZFR0_F32MM 0x1 770#define ID_AA64ZFR0_I8MM 0x1 771#define ID_AA64ZFR0_BF16 0x1 772#define ID_AA64ZFR0_SM4 0x1 773#define ID_AA64ZFR0_SHA3 0x1 774#define ID_AA64ZFR0_BITPERM 0x1 775#define ID_AA64ZFR0_AES 0x1 776#define ID_AA64ZFR0_AES_PMULL 0x2 777#define ID_AA64ZFR0_SVEVER_SVE2 0x1 778 779/* id_aa64mmfr0 */ 780#define ID_AA64MMFR0_ECV_SHIFT 60 781#define ID_AA64MMFR0_FGT_SHIFT 56 782#define ID_AA64MMFR0_EXS_SHIFT 44 783#define ID_AA64MMFR0_TGRAN4_2_SHIFT 40 784#define ID_AA64MMFR0_TGRAN64_2_SHIFT 36 785#define ID_AA64MMFR0_TGRAN16_2_SHIFT 32 786#define ID_AA64MMFR0_TGRAN4_SHIFT 28 787#define ID_AA64MMFR0_TGRAN64_SHIFT 24 788#define ID_AA64MMFR0_TGRAN16_SHIFT 20 789#define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 790#define ID_AA64MMFR0_SNSMEM_SHIFT 12 791#define ID_AA64MMFR0_BIGENDEL_SHIFT 8 792#define ID_AA64MMFR0_ASID_SHIFT 4 793#define ID_AA64MMFR0_PARANGE_SHIFT 0 794 795#define ID_AA64MMFR0_TGRAN4_NI 0xf 796#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 797#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 798#define ID_AA64MMFR0_TGRAN64_NI 0xf 799#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0 800#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7 801#define ID_AA64MMFR0_TGRAN16_NI 0x0 802#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1 803#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf 804 805#define ID_AA64MMFR0_PARANGE_48 0x5 806#define ID_AA64MMFR0_PARANGE_52 0x6 807 808#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0 809#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1 810#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2 811#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX 0x7 812 813#ifdef CONFIG_ARM64_PA_BITS_52 814#define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 815#else 816#define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 817#endif 818 819/* id_aa64mmfr1 */ 820#define ID_AA64MMFR1_ECBHB_SHIFT 60 821#define ID_AA64MMFR1_AFP_SHIFT 44 822#define ID_AA64MMFR1_ETS_SHIFT 36 823#define ID_AA64MMFR1_TWED_SHIFT 32 824#define ID_AA64MMFR1_XNX_SHIFT 28 825#define ID_AA64MMFR1_SPECSEI_SHIFT 24 826#define ID_AA64MMFR1_PAN_SHIFT 20 827#define ID_AA64MMFR1_LOR_SHIFT 16 828#define ID_AA64MMFR1_HPD_SHIFT 12 829#define ID_AA64MMFR1_VHE_SHIFT 8 830#define ID_AA64MMFR1_VMIDBITS_SHIFT 4 831#define ID_AA64MMFR1_HADBS_SHIFT 0 832 833#define ID_AA64MMFR1_VMIDBITS_8 0 834#define ID_AA64MMFR1_VMIDBITS_16 2 835 836/* id_aa64mmfr2 */ 837#define ID_AA64MMFR2_E0PD_SHIFT 60 838#define ID_AA64MMFR2_EVT_SHIFT 56 839#define ID_AA64MMFR2_BBM_SHIFT 52 840#define ID_AA64MMFR2_TTL_SHIFT 48 841#define ID_AA64MMFR2_FWB_SHIFT 40 842#define ID_AA64MMFR2_IDS_SHIFT 36 843#define ID_AA64MMFR2_AT_SHIFT 32 844#define ID_AA64MMFR2_ST_SHIFT 28 845#define ID_AA64MMFR2_NV_SHIFT 24 846#define ID_AA64MMFR2_CCIDX_SHIFT 20 847#define ID_AA64MMFR2_LVA_SHIFT 16 848#define ID_AA64MMFR2_IESB_SHIFT 12 849#define ID_AA64MMFR2_LSM_SHIFT 8 850#define ID_AA64MMFR2_UAO_SHIFT 4 851#define ID_AA64MMFR2_CNP_SHIFT 0 852 853/* id_aa64dfr0 */ 854#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 855#define ID_AA64DFR0_PMSVER_SHIFT 32 856#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 857#define ID_AA64DFR0_WRPS_SHIFT 20 858#define ID_AA64DFR0_BRPS_SHIFT 12 859#define ID_AA64DFR0_PMUVER_SHIFT 8 860#define ID_AA64DFR0_TRACEVER_SHIFT 4 861#define ID_AA64DFR0_DEBUGVER_SHIFT 0 862 863#define ID_AA64DFR0_PMUVER_8_0 0x1 864#define ID_AA64DFR0_PMUVER_8_1 0x4 865#define ID_AA64DFR0_PMUVER_8_4 0x5 866#define ID_AA64DFR0_PMUVER_8_5 0x6 867#define ID_AA64DFR0_PMUVER_IMP_DEF 0xf 868 869#define ID_DFR0_PERFMON_SHIFT 24 870 871#define ID_DFR0_PERFMON_8_1 0x4 872 873#define ID_ISAR4_SWP_FRAC_SHIFT 28 874#define ID_ISAR4_PSR_M_SHIFT 24 875#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20 876#define ID_ISAR4_BARRIER_SHIFT 16 877#define ID_ISAR4_SMC_SHIFT 12 878#define ID_ISAR4_WRITEBACK_SHIFT 8 879#define ID_ISAR4_WITHSHIFTS_SHIFT 4 880#define ID_ISAR4_UNPRIV_SHIFT 0 881 882#define ID_DFR1_MTPMU_SHIFT 0 883 884#define ID_ISAR0_DIVIDE_SHIFT 24 885#define ID_ISAR0_DEBUG_SHIFT 20 886#define ID_ISAR0_COPROC_SHIFT 16 887#define ID_ISAR0_CMPBRANCH_SHIFT 12 888#define ID_ISAR0_BITFIELD_SHIFT 8 889#define ID_ISAR0_BITCOUNT_SHIFT 4 890#define ID_ISAR0_SWAP_SHIFT 0 891 892#define ID_ISAR5_RDM_SHIFT 24 893#define ID_ISAR5_CRC32_SHIFT 16 894#define ID_ISAR5_SHA2_SHIFT 12 895#define ID_ISAR5_SHA1_SHIFT 8 896#define ID_ISAR5_AES_SHIFT 4 897#define ID_ISAR5_SEVL_SHIFT 0 898 899#define ID_ISAR6_I8MM_SHIFT 24 900#define ID_ISAR6_BF16_SHIFT 20 901#define ID_ISAR6_SPECRES_SHIFT 16 902#define ID_ISAR6_SB_SHIFT 12 903#define ID_ISAR6_FHM_SHIFT 8 904#define ID_ISAR6_DP_SHIFT 4 905#define ID_ISAR6_JSCVT_SHIFT 0 906 907#define ID_MMFR0_INNERSHR_SHIFT 28 908#define ID_MMFR0_FCSE_SHIFT 24 909#define ID_MMFR0_AUXREG_SHIFT 20 910#define ID_MMFR0_TCM_SHIFT 16 911#define ID_MMFR0_SHARELVL_SHIFT 12 912#define ID_MMFR0_OUTERSHR_SHIFT 8 913#define ID_MMFR0_PMSA_SHIFT 4 914#define ID_MMFR0_VMSA_SHIFT 0 915 916#define ID_MMFR4_EVT_SHIFT 28 917#define ID_MMFR4_CCIDX_SHIFT 24 918#define ID_MMFR4_LSM_SHIFT 20 919#define ID_MMFR4_HPDS_SHIFT 16 920#define ID_MMFR4_CNP_SHIFT 12 921#define ID_MMFR4_XNX_SHIFT 8 922#define ID_MMFR4_AC2_SHIFT 4 923#define ID_MMFR4_SPECSEI_SHIFT 0 924 925#define ID_MMFR5_ETS_SHIFT 0 926 927#define ID_PFR0_DIT_SHIFT 24 928#define ID_PFR0_CSV2_SHIFT 16 929#define ID_PFR0_STATE3_SHIFT 12 930#define ID_PFR0_STATE2_SHIFT 8 931#define ID_PFR0_STATE1_SHIFT 4 932#define ID_PFR0_STATE0_SHIFT 0 933 934#define ID_DFR0_PERFMON_SHIFT 24 935#define ID_DFR0_MPROFDBG_SHIFT 20 936#define ID_DFR0_MMAPTRC_SHIFT 16 937#define ID_DFR0_COPTRC_SHIFT 12 938#define ID_DFR0_MMAPDBG_SHIFT 8 939#define ID_DFR0_COPSDBG_SHIFT 4 940#define ID_DFR0_COPDBG_SHIFT 0 941 942#define ID_PFR2_SSBS_SHIFT 4 943#define ID_PFR2_CSV3_SHIFT 0 944 945#define MVFR0_FPROUND_SHIFT 28 946#define MVFR0_FPSHVEC_SHIFT 24 947#define MVFR0_FPSQRT_SHIFT 20 948#define MVFR0_FPDIVIDE_SHIFT 16 949#define MVFR0_FPTRAP_SHIFT 12 950#define MVFR0_FPDP_SHIFT 8 951#define MVFR0_FPSP_SHIFT 4 952#define MVFR0_SIMD_SHIFT 0 953 954#define MVFR1_SIMDFMAC_SHIFT 28 955#define MVFR1_FPHP_SHIFT 24 956#define MVFR1_SIMDHP_SHIFT 20 957#define MVFR1_SIMDSP_SHIFT 16 958#define MVFR1_SIMDINT_SHIFT 12 959#define MVFR1_SIMDLS_SHIFT 8 960#define MVFR1_FPDNAN_SHIFT 4 961#define MVFR1_FPFTZ_SHIFT 0 962 963#define ID_PFR1_GIC_SHIFT 28 964#define ID_PFR1_VIRT_FRAC_SHIFT 24 965#define ID_PFR1_SEC_FRAC_SHIFT 20 966#define ID_PFR1_GENTIMER_SHIFT 16 967#define ID_PFR1_VIRTUALIZATION_SHIFT 12 968#define ID_PFR1_MPROGMOD_SHIFT 8 969#define ID_PFR1_SECURITY_SHIFT 4 970#define ID_PFR1_PROGMOD_SHIFT 0 971 972#if defined(CONFIG_ARM64_4K_PAGES) 973#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 974#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 975#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 976#elif defined(CONFIG_ARM64_16K_PAGES) 977#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 978#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 979#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 980#elif defined(CONFIG_ARM64_64K_PAGES) 981#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 982#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 983#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 984#endif 985 986#define MVFR2_FPMISC_SHIFT 4 987#define MVFR2_SIMDMISC_SHIFT 0 988 989#define DCZID_DZP_SHIFT 4 990#define DCZID_BS_SHIFT 0 991 992/* 993 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 994 * are reserved by the SVE architecture for future expansion of the LEN 995 * field, with compatible semantics. 996 */ 997#define ZCR_ELx_LEN_SHIFT 0 998#define ZCR_ELx_LEN_SIZE 9 999#define ZCR_ELx_LEN_MASK 0x1ff 1000 1001#define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 1002#define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 1003#define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 1004 1005/* TCR EL1 Bit Definitions */ 1006#define SYS_TCR_EL1_TCMA1 (BIT(58)) 1007#define SYS_TCR_EL1_TCMA0 (BIT(57)) 1008 1009/* GCR_EL1 Definitions */ 1010#define SYS_GCR_EL1_RRND (BIT(16)) 1011#define SYS_GCR_EL1_EXCL_MASK 0xffffUL 1012 1013/* RGSR_EL1 Definitions */ 1014#define SYS_RGSR_EL1_TAG_MASK 0xfUL 1015#define SYS_RGSR_EL1_SEED_SHIFT 8 1016#define SYS_RGSR_EL1_SEED_MASK 0xffffUL 1017 1018/* GMID_EL1 field definitions */ 1019#define SYS_GMID_EL1_BS_SHIFT 0 1020#define SYS_GMID_EL1_BS_SIZE 4 1021 1022/* TFSR{,E0}_EL1 bit definitions */ 1023#define SYS_TFSR_EL1_TF0_SHIFT 0 1024#define SYS_TFSR_EL1_TF1_SHIFT 1 1025#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) 1026#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) 1027 1028/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 1029#define SYS_MPIDR_SAFE_VAL (BIT(31)) 1030 1031#ifdef __ASSEMBLY__ 1032 1033 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 1034 .equ .L__reg_num_x\num, \num 1035 .endr 1036 .equ .L__reg_num_xzr, 31 1037 1038 .macro mrs_s, rt, sreg 1039 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 1040 .endm 1041 1042 .macro msr_s, sreg, rt 1043 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 1044 .endm 1045 1046#else 1047 1048#include <linux/build_bug.h> 1049#include <linux/types.h> 1050#include <asm/alternative.h> 1051 1052#define __DEFINE_MRS_MSR_S_REGNUM \ 1053" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ 1054" .equ .L__reg_num_x\\num, \\num\n" \ 1055" .endr\n" \ 1056" .equ .L__reg_num_xzr, 31\n" 1057 1058#define DEFINE_MRS_S \ 1059 __DEFINE_MRS_MSR_S_REGNUM \ 1060" .macro mrs_s, rt, sreg\n" \ 1061 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \ 1062" .endm\n" 1063 1064#define DEFINE_MSR_S \ 1065 __DEFINE_MRS_MSR_S_REGNUM \ 1066" .macro msr_s, sreg, rt\n" \ 1067 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \ 1068" .endm\n" 1069 1070#define UNDEFINE_MRS_S \ 1071" .purgem mrs_s\n" 1072 1073#define UNDEFINE_MSR_S \ 1074" .purgem msr_s\n" 1075 1076#define __mrs_s(v, r) \ 1077 DEFINE_MRS_S \ 1078" mrs_s " v ", " __stringify(r) "\n" \ 1079 UNDEFINE_MRS_S 1080 1081#define __msr_s(r, v) \ 1082 DEFINE_MSR_S \ 1083" msr_s " __stringify(r) ", " v "\n" \ 1084 UNDEFINE_MSR_S 1085 1086/* 1087 * Unlike read_cpuid, calls to read_sysreg are never expected to be 1088 * optimized away or replaced with synthetic values. 1089 */ 1090#define read_sysreg(r) ({ \ 1091 u64 __val; \ 1092 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 1093 __val; \ 1094}) 1095 1096/* 1097 * The "Z" constraint normally means a zero immediate, but when combined with 1098 * the "%x0" template means XZR. 1099 */ 1100#define write_sysreg(v, r) do { \ 1101 u64 __val = (u64)(v); \ 1102 asm volatile("msr " __stringify(r) ", %x0" \ 1103 : : "rZ" (__val)); \ 1104} while (0) 1105 1106/* 1107 * For registers without architectural names, or simply unsupported by 1108 * GAS. 1109 */ 1110#define read_sysreg_s(r) ({ \ 1111 u64 __val; \ 1112 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 1113 __val; \ 1114}) 1115 1116#define write_sysreg_s(v, r) do { \ 1117 u64 __val = (u64)(v); \ 1118 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 1119} while (0) 1120 1121/* 1122 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 1123 * set mask are set. Other bits are left as-is. 1124 */ 1125#define sysreg_clear_set(sysreg, clear, set) do { \ 1126 u64 __scs_val = read_sysreg(sysreg); \ 1127 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1128 if (__scs_new != __scs_val) \ 1129 write_sysreg(__scs_new, sysreg); \ 1130} while (0) 1131 1132#define sysreg_clear_set_s(sysreg, clear, set) do { \ 1133 u64 __scs_val = read_sysreg_s(sysreg); \ 1134 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1135 if (__scs_new != __scs_val) \ 1136 write_sysreg_s(__scs_new, sysreg); \ 1137} while (0) 1138 1139#define read_sysreg_par() ({ \ 1140 u64 par; \ 1141 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1142 par = read_sysreg(par_el1); \ 1143 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1144 par; \ 1145}) 1146 1147#endif 1148 1149#endif /* __ASM_SYSREG_H */ 1150