1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/mmu_context.h
4 *
5 * Copyright (C) 1996 Russell King.
6 * Copyright (C) 2012 ARM Ltd.
7 */
8#ifndef __ASM_MMU_CONTEXT_H
9#define __ASM_MMU_CONTEXT_H
10
11#ifndef __ASSEMBLY__
12
13#include <linux/compiler.h>
14#include <linux/sched.h>
15#include <linux/sched/hotplug.h>
16#include <linux/mm_types.h>
17#include <linux/pgtable.h>
18
19#include <asm/cacheflush.h>
20#include <asm/cpufeature.h>
21#include <asm/proc-fns.h>
22#include <asm-generic/mm_hooks.h>
23#include <asm/cputype.h>
24#include <asm/sysreg.h>
25#include <asm/tlbflush.h>
26
27extern bool rodata_full;
28
29static inline void contextidr_thread_switch(struct task_struct *next)
30{
31	if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR))
32		return;
33
34	write_sysreg(task_pid_nr(next), contextidr_el1);
35	isb();
36}
37
38/*
39 * Set TTBR0 to reserved_pg_dir. No translations will be possible via TTBR0.
40 */
41static inline void cpu_set_reserved_ttbr0(void)
42{
43	unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
44
45	write_sysreg(ttbr, ttbr0_el1);
46	isb();
47}
48
49void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
50
51static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm)
52{
53	BUG_ON(pgd == swapper_pg_dir);
54	cpu_set_reserved_ttbr0();
55	cpu_do_switch_mm(virt_to_phys(pgd),mm);
56}
57
58/*
59 * TCR.T0SZ value to use when the ID map is active. Usually equals
60 * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
61 * physical memory, in which case it will be smaller.
62 */
63extern u64 idmap_t0sz;
64extern u64 idmap_ptrs_per_pgd;
65
66static inline bool __cpu_uses_extended_idmap(void)
67{
68	return unlikely(idmap_t0sz != TCR_T0SZ(vabits_actual));
69}
70
71/*
72 * True if the extended ID map requires an extra level of translation table
73 * to be configured.
74 */
75static inline bool __cpu_uses_extended_idmap_level(void)
76{
77	return ARM64_HW_PGTABLE_LEVELS(64 - idmap_t0sz) > CONFIG_PGTABLE_LEVELS;
78}
79
80/*
81 * Set TCR.T0SZ to its default value (based on VA_BITS)
82 */
83static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
84{
85	unsigned long tcr;
86
87	if (!__cpu_uses_extended_idmap())
88		return;
89
90	tcr = read_sysreg(tcr_el1);
91	tcr &= ~TCR_T0SZ_MASK;
92	tcr |= t0sz << TCR_T0SZ_OFFSET;
93	write_sysreg(tcr, tcr_el1);
94	isb();
95}
96
97#define cpu_set_default_tcr_t0sz()	__cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual))
98#define cpu_set_idmap_tcr_t0sz()	__cpu_set_tcr_t0sz(idmap_t0sz)
99
100/*
101 * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm.
102 *
103 * The idmap lives in the same VA range as userspace, but uses global entries
104 * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from
105 * speculative TLB fetches, we must temporarily install the reserved page
106 * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ.
107 *
108 * If current is a not a user task, the mm covers the TTBR1_EL1 page tables,
109 * which should not be installed in TTBR0_EL1. In this case we can leave the
110 * reserved page tables in place.
111 */
112static inline void cpu_uninstall_idmap(void)
113{
114	struct mm_struct *mm = current->active_mm;
115
116	cpu_set_reserved_ttbr0();
117	local_flush_tlb_all();
118	cpu_set_default_tcr_t0sz();
119
120	if (mm != &init_mm && !system_uses_ttbr0_pan())
121		cpu_switch_mm(mm->pgd, mm);
122}
123
124static inline void cpu_install_idmap(void)
125{
126	cpu_set_reserved_ttbr0();
127	local_flush_tlb_all();
128	cpu_set_idmap_tcr_t0sz();
129
130	cpu_switch_mm(lm_alias(idmap_pg_dir), &init_mm);
131}
132
133/*
134 * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
135 * avoiding the possibility of conflicting TLB entries being allocated.
136 */
137static inline void __nocfi cpu_replace_ttbr1(pgd_t *pgdp)
138{
139	typedef void (ttbr_replace_func)(phys_addr_t);
140	extern ttbr_replace_func idmap_cpu_replace_ttbr1;
141	ttbr_replace_func *replace_phys;
142
143	/* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */
144	phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp));
145
146	if (system_supports_cnp() && !WARN_ON(pgdp != lm_alias(swapper_pg_dir))) {
147		/*
148		 * cpu_replace_ttbr1() is used when there's a boot CPU
149		 * up (i.e. cpufeature framework is not up yet) and
150		 * latter only when we enable CNP via cpufeature's
151		 * enable() callback.
152		 * Also we rely on the cpu_hwcap bit being set before
153		 * calling the enable() function.
154		 */
155		ttbr1 |= TTBR_CNP_BIT;
156	}
157
158	replace_phys = (void *)__pa_symbol(function_nocfi(idmap_cpu_replace_ttbr1));
159
160	cpu_install_idmap();
161	replace_phys(ttbr1);
162	cpu_uninstall_idmap();
163}
164
165/*
166 * It would be nice to return ASIDs back to the allocator, but unfortunately
167 * that introduces a race with a generation rollover where we could erroneously
168 * free an ASID allocated in a future generation. We could workaround this by
169 * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
170 * but we'd then need to make sure that we didn't dirty any TLBs afterwards.
171 * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
172 * take CPU migration into account.
173 */
174#define destroy_context(mm)		do { } while(0)
175void check_and_switch_context(struct mm_struct *mm);
176
177static inline int
178init_new_context(struct task_struct *tsk, struct mm_struct *mm)
179{
180	atomic64_set(&mm->context.id, 0);
181	refcount_set(&mm->context.pinned, 0);
182	return 0;
183}
184
185#ifdef CONFIG_ARM64_SW_TTBR0_PAN
186static inline void update_saved_ttbr0(struct task_struct *tsk,
187				      struct mm_struct *mm)
188{
189	u64 ttbr;
190
191	if (!system_uses_ttbr0_pan())
192		return;
193
194	if (mm == &init_mm)
195		ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
196	else
197		ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48;
198
199	WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr);
200}
201#else
202static inline void update_saved_ttbr0(struct task_struct *tsk,
203				      struct mm_struct *mm)
204{
205}
206#endif
207
208static inline void
209enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
210{
211	/*
212	 * We don't actually care about the ttbr0 mapping, so point it at the
213	 * zero page.
214	 */
215	update_saved_ttbr0(tsk, &init_mm);
216}
217
218static inline void __switch_mm(struct mm_struct *next)
219{
220	/*
221	 * init_mm.pgd does not contain any user mappings and it is always
222	 * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
223	 */
224	if (next == &init_mm) {
225		cpu_set_reserved_ttbr0();
226		return;
227	}
228
229	check_and_switch_context(next);
230}
231
232static inline void
233switch_mm(struct mm_struct *prev, struct mm_struct *next,
234	  struct task_struct *tsk)
235{
236	if (prev != next)
237		__switch_mm(next);
238
239	/*
240	 * Update the saved TTBR0_EL1 of the scheduled-in task as the previous
241	 * value may have not been initialised yet (activate_mm caller) or the
242	 * ASID has changed since the last run (following the context switch
243	 * of another thread of the same process).
244	 */
245	update_saved_ttbr0(tsk, next);
246}
247
248#define deactivate_mm(tsk,mm)	do { } while (0)
249#define activate_mm(prev,next)	switch_mm(prev, next, current)
250
251void verify_cpu_asid_bits(void);
252void post_ttbr_update_workaround(void);
253
254unsigned long arm64_mm_context_get(struct mm_struct *mm);
255void arm64_mm_context_put(struct mm_struct *mm);
256
257#endif /* !__ASSEMBLY__ */
258
259#endif /* !__ASM_MMU_CONTEXT_H */
260