1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#ifndef __ARM64_KVM_MMU_H__
8#define __ARM64_KVM_MMU_H__
9
10#include <asm/page.h>
11#include <asm/memory.h>
12#include <asm/mmu.h>
13#include <asm/cpufeature.h>
14
15/*
16 * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express
17 * "negative" addresses. This makes it impossible to directly share
18 * mappings with the kernel.
19 *
20 * Instead, give the HYP mode its own VA region at a fixed offset from
21 * the kernel by just masking the top bits (which are all ones for a
22 * kernel address). We need to find out how many bits to mask.
23 *
24 * We want to build a set of page tables that cover both parts of the
25 * idmap (the trampoline page used to initialize EL2), and our normal
26 * runtime VA space, at the same time.
27 *
28 * Given that the kernel uses VA_BITS for its entire address space,
29 * and that half of that space (VA_BITS - 1) is used for the linear
30 * mapping, we can also limit the EL2 space to (VA_BITS - 1).
31 *
32 * The main question is "Within the VA_BITS space, does EL2 use the
33 * top or the bottom half of that space to shadow the kernel's linear
34 * mapping?". As we need to idmap the trampoline page, this is
35 * determined by the range in which this page lives.
36 *
37 * If the page is in the bottom half, we have to use the top half. If
38 * the page is in the top half, we have to use the bottom half:
39 *
40 * T = __pa_symbol(__hyp_idmap_text_start)
41 * if (T & BIT(VA_BITS - 1))
42 *	HYP_VA_MIN = 0  //idmap in upper half
43 * else
44 *	HYP_VA_MIN = 1 << (VA_BITS - 1)
45 * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1
46 *
47 * When using VHE, there are no separate hyp mappings and all KVM
48 * functionality is already mapped as part of the main kernel
49 * mappings, and none of this applies in that case.
50 */
51
52#ifdef __ASSEMBLY__
53
54#include <asm/alternative.h>
55
56/*
57 * Convert a kernel VA into a HYP VA.
58 * reg: VA to be converted.
59 *
60 * The actual code generation takes place in kvm_update_va_mask, and
61 * the instructions below are only there to reserve the space and
62 * perform the register allocation (kvm_update_va_mask uses the
63 * specific registers encoded in the instructions).
64 */
65.macro kern_hyp_va	reg
66alternative_cb kvm_update_va_mask
67	and     \reg, \reg, #1		/* mask with va_mask */
68	ror	\reg, \reg, #1		/* rotate to the first tag bit */
69	add	\reg, \reg, #0		/* insert the low 12 bits of the tag */
70	add	\reg, \reg, #0, lsl 12	/* insert the top 12 bits of the tag */
71	ror	\reg, \reg, #63		/* rotate back */
72alternative_cb_end
73.endm
74
75#else
76
77#include <linux/pgtable.h>
78#include <asm/pgalloc.h>
79#include <asm/cache.h>
80#include <asm/cacheflush.h>
81#include <asm/mmu_context.h>
82
83void kvm_update_va_mask(struct alt_instr *alt,
84			__le32 *origptr, __le32 *updptr, int nr_inst);
85void kvm_compute_layout(void);
86
87static __always_inline unsigned long __kern_hyp_va(unsigned long v)
88{
89	asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n"
90				    "ror %0, %0, #1\n"
91				    "add %0, %0, #0\n"
92				    "add %0, %0, #0, lsl 12\n"
93				    "ror %0, %0, #63\n",
94				    kvm_update_va_mask)
95		     : "+r" (v));
96	return v;
97}
98
99#define kern_hyp_va(v) 	((typeof(v))(__kern_hyp_va((unsigned long)(v))))
100
101/*
102 * We currently support using a VM-specified IPA size. For backward
103 * compatibility, the default IPA size is fixed to 40bits.
104 */
105#define KVM_PHYS_SHIFT	(40)
106
107#define kvm_phys_shift(kvm)		VTCR_EL2_IPA(kvm->arch.vtcr)
108#define kvm_phys_size(kvm)		(_AC(1, ULL) << kvm_phys_shift(kvm))
109#define kvm_phys_mask(kvm)		(kvm_phys_size(kvm) - _AC(1, ULL))
110
111#include <asm/kvm_pgtable.h>
112#include <asm/stage2_pgtable.h>
113
114int create_hyp_mappings(void *from, void *to, enum kvm_pgtable_prot prot);
115int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
116			   void __iomem **kaddr,
117			   void __iomem **haddr);
118int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
119			     void **haddr);
120void free_hyp_pgds(void);
121
122void stage2_unmap_vm(struct kvm *kvm);
123int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu);
124void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu);
125int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
126			  phys_addr_t pa, unsigned long size, bool writable);
127
128int kvm_handle_guest_abort(struct kvm_vcpu *vcpu);
129
130phys_addr_t kvm_mmu_get_httbr(void);
131phys_addr_t kvm_get_idmap_vector(void);
132int kvm_mmu_init(void);
133
134struct kvm;
135
136#define kvm_flush_dcache_to_poc(a,l)	__flush_dcache_area((a), (l))
137
138static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
139{
140	return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
141}
142
143static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size)
144{
145	void *va = page_address(pfn_to_page(pfn));
146
147	/*
148	 * With FWB, we ensure that the guest always accesses memory using
149	 * cacheable attributes, and we don't have to clean to PoC when
150	 * faulting in pages. Furthermore, FWB implies IDC, so cleaning to
151	 * PoU is not required either in this case.
152	 */
153	if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
154		return;
155
156	kvm_flush_dcache_to_poc(va, size);
157}
158
159static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn,
160						  unsigned long size)
161{
162	if (icache_is_aliasing()) {
163		/* any kind of VIPT cache */
164		__flush_icache_all();
165	} else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) {
166		/* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */
167		void *va = page_address(pfn_to_page(pfn));
168
169		invalidate_icache_range((unsigned long)va,
170					(unsigned long)va + size);
171	}
172}
173
174void kvm_set_way_flush(struct kvm_vcpu *vcpu);
175void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
176
177static inline unsigned int kvm_get_vmid_bits(void)
178{
179	int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
180
181	return get_vmid_bits(reg);
182}
183
184/*
185 * We are not in the kvm->srcu critical section most of the time, so we take
186 * the SRCU read lock here. Since we copy the data from the user page, we
187 * can immediately drop the lock again.
188 */
189static inline int kvm_read_guest_lock(struct kvm *kvm,
190				      gpa_t gpa, void *data, unsigned long len)
191{
192	int srcu_idx = srcu_read_lock(&kvm->srcu);
193	int ret = kvm_read_guest(kvm, gpa, data, len);
194
195	srcu_read_unlock(&kvm->srcu, srcu_idx);
196
197	return ret;
198}
199
200static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
201				       const void *data, unsigned long len)
202{
203	int srcu_idx = srcu_read_lock(&kvm->srcu);
204	int ret = kvm_write_guest(kvm, gpa, data, len);
205
206	srcu_read_unlock(&kvm->srcu, srcu_idx);
207
208	return ret;
209}
210
211/*
212 * EL2 vectors can be mapped and rerouted in a number of ways,
213 * depending on the kernel configuration and CPU present:
214 *
215 * - If the CPU is affected by Spectre-v2, the hardening sequence is
216 *   placed in one of the vector slots, which is executed before jumping
217 *   to the real vectors.
218 *
219 * - If the CPU also has the ARM64_HARDEN_EL2_VECTORS cap, the slot
220 *   containing the hardening sequence is mapped next to the idmap page,
221 *   and executed before jumping to the real vectors.
222 *
223 * - If the CPU only has the ARM64_HARDEN_EL2_VECTORS cap, then an
224 *   empty slot is selected, mapped next to the idmap page, and
225 *   executed before jumping to the real vectors.
226 *
227 * Note that ARM64_HARDEN_EL2_VECTORS is somewhat incompatible with
228 * VHE, as we don't have hypervisor-specific mappings. If the system
229 * is VHE and yet selects this capability, it will be ignored.
230 */
231extern void *__kvm_bp_vect_base;
232extern int __kvm_harden_el2_vector_slot;
233
234static inline void *kvm_get_hyp_vector(void)
235{
236	struct bp_hardening_data *data = arm64_get_bp_hardening_data();
237	void *vect = kern_hyp_va(kvm_ksym_ref(__kvm_hyp_vector));
238	int slot = -1;
239
240	if ((cpus_have_const_cap(ARM64_SPECTRE_V2) ||
241	     cpus_have_const_cap(ARM64_SPECTRE_BHB)) && data->template_start) {
242		vect = kern_hyp_va(kvm_ksym_ref(__bp_harden_hyp_vecs));
243		slot = data->hyp_vectors_slot;
244	}
245
246	if (this_cpu_has_cap(ARM64_HARDEN_EL2_VECTORS) && !has_vhe()) {
247		vect = __kvm_bp_vect_base;
248		if (slot == -1)
249			slot = __kvm_harden_el2_vector_slot;
250	}
251
252	if (slot != -1)
253		vect += slot * SZ_2K;
254
255	return vect;
256}
257
258#define kvm_phys_to_vttbr(addr)		phys_to_ttbr(addr)
259
260static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu)
261{
262	struct kvm_vmid *vmid = &mmu->vmid;
263	u64 vmid_field, baddr;
264	u64 cnp = system_supports_cnp() ? VTTBR_CNP_BIT : 0;
265
266	baddr = mmu->pgd_phys;
267	vmid_field = (u64)vmid->vmid << VTTBR_VMID_SHIFT;
268	return kvm_phys_to_vttbr(baddr) | vmid_field | cnp;
269}
270
271/*
272 * Must be called from hyp code running at EL2 with an updated VTTBR
273 * and interrupts disabled.
274 */
275static __always_inline void __load_guest_stage2(struct kvm_s2_mmu *mmu)
276{
277	write_sysreg(kern_hyp_va(mmu->kvm)->arch.vtcr, vtcr_el2);
278	write_sysreg(kvm_get_vttbr(mmu), vttbr_el2);
279
280	/*
281	 * ARM errata 1165522 and 1530923 require the actual execution of the
282	 * above before we can switch to the EL1/EL0 translation regime used by
283	 * the guest.
284	 */
285	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
286}
287
288#endif /* __ASSEMBLY__ */
289#endif /* __ARM64_KVM_MMU_H__ */
290