1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7#ifndef __ASM_ESR_H 8#define __ASM_ESR_H 9 10#include <asm/memory.h> 11#include <asm/sysreg.h> 12 13#define ESR_ELx_EC_UNKNOWN (0x00) 14#define ESR_ELx_EC_WFx (0x01) 15/* Unallocated EC: 0x02 */ 16#define ESR_ELx_EC_CP15_32 (0x03) 17#define ESR_ELx_EC_CP15_64 (0x04) 18#define ESR_ELx_EC_CP14_MR (0x05) 19#define ESR_ELx_EC_CP14_LS (0x06) 20#define ESR_ELx_EC_FP_ASIMD (0x07) 21#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */ 22#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */ 23/* Unallocated EC: 0x0A - 0x0B */ 24#define ESR_ELx_EC_CP14_64 (0x0C) 25#define ESR_ELx_EC_BTI (0x0D) 26#define ESR_ELx_EC_ILL (0x0E) 27/* Unallocated EC: 0x0F - 0x10 */ 28#define ESR_ELx_EC_SVC32 (0x11) 29#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */ 30#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */ 31/* Unallocated EC: 0x14 */ 32#define ESR_ELx_EC_SVC64 (0x15) 33#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */ 34#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */ 35#define ESR_ELx_EC_SYS64 (0x18) 36#define ESR_ELx_EC_SVE (0x19) 37#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */ 38/* Unallocated EC: 0x1B */ 39#define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */ 40/* Unallocated EC: 0x1D - 0x1E */ 41#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */ 42#define ESR_ELx_EC_IABT_LOW (0x20) 43#define ESR_ELx_EC_IABT_CUR (0x21) 44#define ESR_ELx_EC_PC_ALIGN (0x22) 45/* Unallocated EC: 0x23 */ 46#define ESR_ELx_EC_DABT_LOW (0x24) 47#define ESR_ELx_EC_DABT_CUR (0x25) 48#define ESR_ELx_EC_SP_ALIGN (0x26) 49/* Unallocated EC: 0x27 */ 50#define ESR_ELx_EC_FP_EXC32 (0x28) 51/* Unallocated EC: 0x29 - 0x2B */ 52#define ESR_ELx_EC_FP_EXC64 (0x2C) 53/* Unallocated EC: 0x2D - 0x2E */ 54#define ESR_ELx_EC_SERROR (0x2F) 55#define ESR_ELx_EC_BREAKPT_LOW (0x30) 56#define ESR_ELx_EC_BREAKPT_CUR (0x31) 57#define ESR_ELx_EC_SOFTSTP_LOW (0x32) 58#define ESR_ELx_EC_SOFTSTP_CUR (0x33) 59#define ESR_ELx_EC_WATCHPT_LOW (0x34) 60#define ESR_ELx_EC_WATCHPT_CUR (0x35) 61/* Unallocated EC: 0x36 - 0x37 */ 62#define ESR_ELx_EC_BKPT32 (0x38) 63/* Unallocated EC: 0x39 */ 64#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */ 65/* Unallocated EC: 0x3B */ 66#define ESR_ELx_EC_BRK64 (0x3C) 67/* Unallocated EC: 0x3D - 0x3F */ 68#define ESR_ELx_EC_MAX (0x3F) 69 70#define ESR_ELx_EC_SHIFT (26) 71#define ESR_ELx_EC_WIDTH (6) 72#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 73#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 74 75#define ESR_ELx_IL_SHIFT (25) 76#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 77#define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) 78 79/* ISS field definitions shared by different classes */ 80#define ESR_ELx_WNR_SHIFT (6) 81#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 82 83/* Asynchronous Error Type */ 84#define ESR_ELx_IDS_SHIFT (24) 85#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) 86#define ESR_ELx_AET_SHIFT (10) 87#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) 88 89#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) 90#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) 91#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) 92#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) 93#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) 94 95/* Shared ISS field definitions for Data/Instruction aborts */ 96#define ESR_ELx_SET_SHIFT (11) 97#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 98#define ESR_ELx_FnV_SHIFT (10) 99#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 100#define ESR_ELx_EA_SHIFT (9) 101#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 102#define ESR_ELx_S1PTW_SHIFT (7) 103#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 104 105/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 106#define ESR_ELx_FSC (0x3F) 107#define ESR_ELx_FSC_TYPE (0x3C) 108#define ESR_ELx_FSC_LEVEL (0x03) 109#define ESR_ELx_FSC_EXTABT (0x10) 110#define ESR_ELx_FSC_SERROR (0x11) 111#define ESR_ELx_FSC_ACCESS (0x08) 112#define ESR_ELx_FSC_FAULT (0x04) 113#define ESR_ELx_FSC_PERM (0x0C) 114 115/* ISS field definitions for Data Aborts */ 116#define ESR_ELx_ISV_SHIFT (24) 117#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 118#define ESR_ELx_SAS_SHIFT (22) 119#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 120#define ESR_ELx_SSE_SHIFT (21) 121#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 122#define ESR_ELx_SRT_SHIFT (16) 123#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 124#define ESR_ELx_SF_SHIFT (15) 125#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 126#define ESR_ELx_AR_SHIFT (14) 127#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 128#define ESR_ELx_CM_SHIFT (8) 129#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 130 131/* ISS field definitions for exceptions taken in to Hyp */ 132#define ESR_ELx_CV (UL(1) << 24) 133#define ESR_ELx_COND_SHIFT (20) 134#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 135#define ESR_ELx_WFx_ISS_TI (UL(1) << 0) 136#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) 137#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 138#define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) 139 140#define DISR_EL1_IDS (UL(1) << 24) 141/* 142 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean 143 * different things in the future... 144 */ 145#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 146 147/* ESR value templates for specific events */ 148#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI) 149#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 150 ESR_ELx_WFx_ISS_WFI) 151 152/* BRK instruction trap from AArch64 state */ 153#define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff 154 155/* ISS field definitions for System instruction traps */ 156#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 157#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 158#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 159#define ESR_ELx_SYS64_ISS_DIR_READ 0x1 160#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 161 162#define ESR_ELx_SYS64_ISS_RT_SHIFT 5 163#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 164#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 165#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 166#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 167#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 168#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 169#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 170#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 171#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 172#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 173#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 174#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 175 ESR_ELx_SYS64_ISS_OP1_MASK | \ 176 ESR_ELx_SYS64_ISS_OP2_MASK | \ 177 ESR_ELx_SYS64_ISS_CRN_MASK | \ 178 ESR_ELx_SYS64_ISS_CRM_MASK) 179#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 180 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 181 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 182 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 183 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 184 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 185 186#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 187 ESR_ELx_SYS64_ISS_DIR_MASK) 188#define ESR_ELx_SYS64_ISS_RT(esr) \ 189 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) 190/* 191 * User space cache operations have the following sysreg encoding 192 * in System instructions. 193 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) 194 */ 195#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 196#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 197#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 198#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 199#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 200#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 201 202#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 203 ESR_ELx_SYS64_ISS_OP1_MASK | \ 204 ESR_ELx_SYS64_ISS_OP2_MASK | \ 205 ESR_ELx_SYS64_ISS_CRN_MASK | \ 206 ESR_ELx_SYS64_ISS_DIR_MASK) 207#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 208 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 209 ESR_ELx_SYS64_ISS_DIR_WRITE) 210/* 211 * User space MRS operations which are supported for emulation 212 * have the following sysreg encoding in System instructions. 213 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) 214 */ 215#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 216 ESR_ELx_SYS64_ISS_OP1_MASK | \ 217 ESR_ELx_SYS64_ISS_CRN_MASK | \ 218 ESR_ELx_SYS64_ISS_DIR_MASK) 219#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ 220 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ 221 ESR_ELx_SYS64_ISS_DIR_READ) 222 223#define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 224#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 225 ESR_ELx_SYS64_ISS_DIR_READ) 226 227#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 228 ESR_ELx_SYS64_ISS_DIR_READ) 229 230#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 231 ESR_ELx_SYS64_ISS_DIR_READ) 232 233#define esr_sys64_to_sysreg(e) \ 234 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 235 ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 236 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 237 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 238 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 239 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 240 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 241 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 242 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 243 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 244 245#define esr_cp15_to_sysreg(e) \ 246 sys_reg(3, \ 247 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 248 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 249 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 250 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 251 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 252 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 253 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 254 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 255 256/* 257 * ISS field definitions for floating-point exception traps 258 * (FP_EXC_32/FP_EXC_64). 259 * 260 * (The FPEXC_* constants are used instead for common bits.) 261 */ 262 263#define ESR_ELx_FP_EXC_TFV (UL(1) << 23) 264 265/* 266 * ISS field definitions for CP15 accesses 267 */ 268#define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 269#define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 270#define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 271 272#define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 273#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) 274#define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 275#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) 276#define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 277#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) 278#define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 279#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) 280#define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 281#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) 282 283#define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ 284 ESR_ELx_CP15_32_ISS_OP2_MASK | \ 285 ESR_ELx_CP15_32_ISS_CRN_MASK | \ 286 ESR_ELx_CP15_32_ISS_CRM_MASK | \ 287 ESR_ELx_CP15_32_ISS_DIR_MASK) 288#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ 289 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ 290 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ 291 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ 292 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) 293 294#define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 295#define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 296#define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 297 298#define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 299#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) 300 301#define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 302#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) 303 304#define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 305#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) 306#define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 307#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) 308 309#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ 310 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ 311 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) 312 313#define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ 314 ESR_ELx_CP15_64_ISS_CRM_MASK | \ 315 ESR_ELx_CP15_64_ISS_DIR_MASK) 316 317#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ 318 ESR_ELx_CP15_64_ISS_DIR_READ) 319 320#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ 321 ESR_ELx_CP15_32_ISS_DIR_READ) 322 323#ifndef __ASSEMBLY__ 324#include <asm/types.h> 325 326static inline bool esr_is_data_abort(u32 esr) 327{ 328 const u32 ec = ESR_ELx_EC(esr); 329 330 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 331} 332 333const char *esr_get_class_string(u32 esr); 334#endif /* __ASSEMBLY */ 335 336#endif /* __ASM_ESR_H */ 337