1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org> 4 */ 5 6#ifndef __ASM_CPUFEATURE_H 7#define __ASM_CPUFEATURE_H 8 9#include <asm/cpucaps.h> 10#include <asm/cputype.h> 11#include <asm/hwcap.h> 12#include <asm/sysreg.h> 13 14#define MAX_CPU_FEATURES 64 15#define cpu_feature(x) KERNEL_HWCAP_ ## x 16 17#ifndef __ASSEMBLY__ 18 19#include <linux/bug.h> 20#include <linux/jump_label.h> 21#include <linux/kernel.h> 22 23/* 24 * CPU feature register tracking 25 * 26 * The safe value of a CPUID feature field is dependent on the implications 27 * of the values assigned to it by the architecture. Based on the relationship 28 * between the values, the features are classified into 3 types - LOWER_SAFE, 29 * HIGHER_SAFE and EXACT. 30 * 31 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest 32 * for HIGHER_SAFE. It is expected that all CPUs have the same value for 33 * a field when EXACT is specified, failing which, the safe value specified 34 * in the table is chosen. 35 */ 36 37enum ftr_type { 38 FTR_EXACT, /* Use a predefined safe value */ 39 FTR_LOWER_SAFE, /* Smaller value is safe */ 40 FTR_HIGHER_SAFE, /* Bigger value is safe */ 41 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ 42}; 43 44#define FTR_STRICT true /* SANITY check strict matching required */ 45#define FTR_NONSTRICT false /* SANITY check ignored */ 46 47#define FTR_SIGNED true /* Value should be treated as signed */ 48#define FTR_UNSIGNED false /* Value should be treated as unsigned */ 49 50#define FTR_VISIBLE true /* Feature visible to the user space */ 51#define FTR_HIDDEN false /* Feature is hidden from the user */ 52 53#define FTR_VISIBLE_IF_IS_ENABLED(config) \ 54 (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN) 55 56struct arm64_ftr_bits { 57 bool sign; /* Value is signed ? */ 58 bool visible; 59 bool strict; /* CPU Sanity check: strict matching required ? */ 60 enum ftr_type type; 61 u8 shift; 62 u8 width; 63 s64 safe_val; /* safe value for FTR_EXACT features */ 64}; 65 66/* 67 * @arm64_ftr_reg - Feature register 68 * @strict_mask Bits which should match across all CPUs for sanity. 69 * @sys_val Safe value across the CPUs (system view) 70 */ 71struct arm64_ftr_reg { 72 const char *name; 73 u64 strict_mask; 74 u64 user_mask; 75 u64 sys_val; 76 u64 user_val; 77 const struct arm64_ftr_bits *ftr_bits; 78}; 79 80extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; 81 82/* 83 * CPU capabilities: 84 * 85 * We use arm64_cpu_capabilities to represent system features, errata work 86 * arounds (both used internally by kernel and tracked in cpu_hwcaps) and 87 * ELF HWCAPs (which are exposed to user). 88 * 89 * To support systems with heterogeneous CPUs, we need to make sure that we 90 * detect the capabilities correctly on the system and take appropriate 91 * measures to ensure there are no incompatibilities. 92 * 93 * This comment tries to explain how we treat the capabilities. 94 * Each capability has the following list of attributes : 95 * 96 * 1) Scope of Detection : The system detects a given capability by 97 * performing some checks at runtime. This could be, e.g, checking the 98 * value of a field in CPU ID feature register or checking the cpu 99 * model. The capability provides a call back ( @matches() ) to 100 * perform the check. Scope defines how the checks should be performed. 101 * There are three cases: 102 * 103 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one 104 * matches. This implies, we have to run the check on all the 105 * booting CPUs, until the system decides that state of the 106 * capability is finalised. (See section 2 below) 107 * Or 108 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs 109 * matches. This implies, we run the check only once, when the 110 * system decides to finalise the state of the capability. If the 111 * capability relies on a field in one of the CPU ID feature 112 * registers, we use the sanitised value of the register from the 113 * CPU feature infrastructure to make the decision. 114 * Or 115 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the 116 * feature. This category is for features that are "finalised" 117 * (or used) by the kernel very early even before the SMP cpus 118 * are brought up. 119 * 120 * The process of detection is usually denoted by "update" capability 121 * state in the code. 122 * 123 * 2) Finalise the state : The kernel should finalise the state of a 124 * capability at some point during its execution and take necessary 125 * actions if any. Usually, this is done, after all the boot-time 126 * enabled CPUs are brought up by the kernel, so that it can make 127 * better decision based on the available set of CPUs. However, there 128 * are some special cases, where the action is taken during the early 129 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with 130 * Virtualisation Host Extensions). The kernel usually disallows any 131 * changes to the state of a capability once it finalises the capability 132 * and takes any action, as it may be impossible to execute the actions 133 * safely. A CPU brought up after a capability is "finalised" is 134 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary 135 * CPUs are treated "late CPUs" for capabilities determined by the boot 136 * CPU. 137 * 138 * At the moment there are two passes of finalising the capabilities. 139 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via 140 * setup_boot_cpu_capabilities(). 141 * b) Everything except (a) - Run via setup_system_capabilities(). 142 * 143 * 3) Verification: When a CPU is brought online (e.g, by user or by the 144 * kernel), the kernel should make sure that it is safe to use the CPU, 145 * by verifying that the CPU is compliant with the state of the 146 * capabilities finalised already. This happens via : 147 * 148 * secondary_start_kernel()-> check_local_cpu_capabilities() 149 * 150 * As explained in (2) above, capabilities could be finalised at 151 * different points in the execution. Each newly booted CPU is verified 152 * against the capabilities that have been finalised by the time it 153 * boots. 154 * 155 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability 156 * except for the primary boot CPU. 157 * 158 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the 159 * user after the kernel boot are verified against the capability. 160 * 161 * If there is a conflict, the kernel takes an action, based on the 162 * severity (e.g, a CPU could be prevented from booting or cause a 163 * kernel panic). The CPU is allowed to "affect" the state of the 164 * capability, if it has not been finalised already. See section 5 165 * for more details on conflicts. 166 * 167 * 4) Action: As mentioned in (2), the kernel can take an action for each 168 * detected capability, on all CPUs on the system. Appropriate actions 169 * include, turning on an architectural feature, modifying the control 170 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via 171 * alternatives. The kernel patching is batched and performed at later 172 * point. The actions are always initiated only after the capability 173 * is finalised. This is usally denoted by "enabling" the capability. 174 * The actions are initiated as follows : 175 * a) Action is triggered on all online CPUs, after the capability is 176 * finalised, invoked within the stop_machine() context from 177 * enable_cpu_capabilitie(). 178 * 179 * b) Any late CPU, brought up after (1), the action is triggered via: 180 * 181 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities() 182 * 183 * 5) Conflicts: Based on the state of the capability on a late CPU vs. 184 * the system state, we could have the following combinations : 185 * 186 * x-----------------------------x 187 * | Type | System | Late CPU | 188 * |-----------------------------| 189 * | a | y | n | 190 * |-----------------------------| 191 * | b | n | y | 192 * x-----------------------------x 193 * 194 * Two separate flag bits are defined to indicate whether each kind of 195 * conflict can be allowed: 196 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed 197 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed 198 * 199 * Case (a) is not permitted for a capability that the system requires 200 * all CPUs to have in order for the capability to be enabled. This is 201 * typical for capabilities that represent enhanced functionality. 202 * 203 * Case (b) is not permitted for a capability that must be enabled 204 * during boot if any CPU in the system requires it in order to run 205 * safely. This is typical for erratum work arounds that cannot be 206 * enabled after the corresponding capability is finalised. 207 * 208 * In some non-typical cases either both (a) and (b), or neither, 209 * should be permitted. This can be described by including neither 210 * or both flags in the capability's type field. 211 * 212 * In case of a conflict, the CPU is prevented from booting. If the 213 * ARM64_CPUCAP_PANIC_ON_CONFLICT flag is specified for the capability, 214 * then a kernel panic is triggered. 215 */ 216 217 218/* 219 * Decide how the capability is detected. 220 * On any local CPU vs System wide vs the primary boot CPU 221 */ 222#define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0)) 223#define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1)) 224/* 225 * The capabilitiy is detected on the Boot CPU and is used by kernel 226 * during early boot. i.e, the capability should be "detected" and 227 * "enabled" as early as possibly on all booting CPUs. 228 */ 229#define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2)) 230#define ARM64_CPUCAP_SCOPE_MASK \ 231 (ARM64_CPUCAP_SCOPE_SYSTEM | \ 232 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 233 ARM64_CPUCAP_SCOPE_BOOT_CPU) 234 235#define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM 236#define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU 237#define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU 238#define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK 239 240/* 241 * Is it permitted for a late CPU to have this capability when system 242 * hasn't already enabled it ? 243 */ 244#define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4)) 245/* Is it safe for a late CPU to miss this capability when system has it */ 246#define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5)) 247/* Panic when a conflict is detected */ 248#define ARM64_CPUCAP_PANIC_ON_CONFLICT ((u16)BIT(6)) 249 250/* 251 * CPU errata workarounds that need to be enabled at boot time if one or 252 * more CPUs in the system requires it. When one of these capabilities 253 * has been enabled, it is safe to allow any CPU to boot that doesn't 254 * require the workaround. However, it is not safe if a "late" CPU 255 * requires a workaround and the system hasn't enabled it already. 256 */ 257#define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \ 258 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU) 259/* 260 * CPU feature detected at boot time based on system-wide value of a 261 * feature. It is safe for a late CPU to have this feature even though 262 * the system hasn't enabled it, although the feature will not be used 263 * by Linux in this case. If the system has enabled this feature already, 264 * then every late CPU must have it. 265 */ 266#define ARM64_CPUCAP_SYSTEM_FEATURE \ 267 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 268/* 269 * CPU feature detected at boot time based on feature of one or more CPUs. 270 * All possible conflicts for a late CPU are ignored. 271 * NOTE: this means that a late CPU with the feature will *not* cause the 272 * capability to be advertised by cpus_have_*cap()! 273 */ 274#define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \ 275 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 276 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \ 277 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 278 279/* 280 * CPU feature detected at boot time, on one or more CPUs. A late CPU 281 * is not allowed to have the capability when the system doesn't have it. 282 * It is Ok for a late CPU to miss the feature. 283 */ 284#define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \ 285 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 286 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU) 287 288/* 289 * CPU feature used early in the boot based on the boot CPU. All secondary 290 * CPUs must match the state of the capability as detected by the boot CPU. In 291 * case of a conflict, a kernel panic is triggered. 292 */ 293#define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE \ 294 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT) 295 296/* 297 * CPU feature used early in the boot based on the boot CPU. It is safe for a 298 * late CPU to have this feature even though the boot CPU hasn't enabled it, 299 * although the feature will not be used by Linux in this case. If the boot CPU 300 * has enabled this feature already, then every late CPU must have it. 301 */ 302#define ARM64_CPUCAP_BOOT_CPU_FEATURE \ 303 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 304 305struct arm64_cpu_capabilities { 306 const char *desc; 307 u16 capability; 308 u16 type; 309 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); 310 /* 311 * Take the appropriate actions to configure this capability 312 * for this CPU. If the capability is detected by the kernel 313 * this will be called on all the CPUs in the system, 314 * including the hotplugged CPUs, regardless of whether the 315 * capability is available on that specific CPU. This is 316 * useful for some capabilities (e.g, working around CPU 317 * errata), where all the CPUs must take some action (e.g, 318 * changing system control/configuration). Thus, if an action 319 * is required only if the CPU has the capability, then the 320 * routine must check it before taking any action. 321 */ 322 void (*cpu_enable)(const struct arm64_cpu_capabilities *cap); 323 union { 324 struct { /* To be used for erratum handling only */ 325 struct midr_range midr_range; 326 const struct arm64_midr_revidr { 327 u32 midr_rv; /* revision/variant */ 328 u32 revidr_mask; 329 } * const fixed_revs; 330 }; 331 332 const struct midr_range *midr_range_list; 333 struct { /* Feature register checking */ 334 u32 sys_reg; 335 u8 field_pos; 336 u8 min_field_value; 337 u8 hwcap_type; 338 bool sign; 339 unsigned long hwcap; 340 }; 341 }; 342 343 /* 344 * An optional list of "matches/cpu_enable" pair for the same 345 * "capability" of the same "type" as described by the parent. 346 * Only matches(), cpu_enable() and fields relevant to these 347 * methods are significant in the list. The cpu_enable is 348 * invoked only if the corresponding entry "matches()". 349 * However, if a cpu_enable() method is associated 350 * with multiple matches(), care should be taken that either 351 * the match criteria are mutually exclusive, or that the 352 * method is robust against being called multiple times. 353 */ 354 const struct arm64_cpu_capabilities *match_list; 355}; 356 357static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap) 358{ 359 return cap->type & ARM64_CPUCAP_SCOPE_MASK; 360} 361 362/* 363 * Generic helper for handling capabilities with multiple (match,enable) pairs 364 * of call backs, sharing the same capability bit. 365 * Iterate over each entry to see if at least one matches. 366 */ 367static inline bool 368cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, 369 int scope) 370{ 371 const struct arm64_cpu_capabilities *caps; 372 373 for (caps = entry->match_list; caps->matches; caps++) 374 if (caps->matches(caps, scope)) 375 return true; 376 377 return false; 378} 379 380static __always_inline bool is_vhe_hyp_code(void) 381{ 382 /* Only defined for code run in VHE hyp context */ 383 return __is_defined(__KVM_VHE_HYPERVISOR__); 384} 385 386static __always_inline bool is_nvhe_hyp_code(void) 387{ 388 /* Only defined for code run in NVHE hyp context */ 389 return __is_defined(__KVM_NVHE_HYPERVISOR__); 390} 391 392static __always_inline bool is_hyp_code(void) 393{ 394 return is_vhe_hyp_code() || is_nvhe_hyp_code(); 395} 396 397extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 398extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS]; 399extern struct static_key_false arm64_const_caps_ready; 400 401/* ARM64 CAPS + alternative_cb */ 402#define ARM64_NPATCHABLE (ARM64_NCAPS + 1) 403extern DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 404 405#define for_each_available_cap(cap) \ 406 for_each_set_bit(cap, cpu_hwcaps, ARM64_NCAPS) 407 408bool this_cpu_has_cap(unsigned int cap); 409void cpu_set_feature(unsigned int num); 410bool cpu_have_feature(unsigned int num); 411unsigned long cpu_get_elf_hwcap(void); 412unsigned long cpu_get_elf_hwcap2(void); 413 414#define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name)) 415#define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name)) 416 417static __always_inline bool system_capabilities_finalized(void) 418{ 419 return static_branch_likely(&arm64_const_caps_ready); 420} 421 422/* 423 * Test for a capability with a runtime check. 424 * 425 * Before the capability is detected, this returns false. 426 */ 427static inline bool cpus_have_cap(unsigned int num) 428{ 429 if (num >= ARM64_NCAPS) 430 return false; 431 return test_bit(num, cpu_hwcaps); 432} 433 434/* 435 * Test for a capability without a runtime check. 436 * 437 * Before capabilities are finalized, this returns false. 438 * After capabilities are finalized, this is patched to avoid a runtime check. 439 * 440 * @num must be a compile-time constant. 441 */ 442static __always_inline bool __cpus_have_const_cap(int num) 443{ 444 if (num >= ARM64_NCAPS) 445 return false; 446 return static_branch_unlikely(&cpu_hwcap_keys[num]); 447} 448 449/* 450 * Test for a capability without a runtime check. 451 * 452 * Before capabilities are finalized, this will BUG(). 453 * After capabilities are finalized, this is patched to avoid a runtime check. 454 * 455 * @num must be a compile-time constant. 456 */ 457static __always_inline bool cpus_have_final_cap(int num) 458{ 459 if (system_capabilities_finalized()) 460 return __cpus_have_const_cap(num); 461 else 462 BUG(); 463} 464 465/* 466 * Test for a capability, possibly with a runtime check for non-hyp code. 467 * 468 * For hyp code, this behaves the same as cpus_have_final_cap(). 469 * 470 * For non-hyp code: 471 * Before capabilities are finalized, this behaves as cpus_have_cap(). 472 * After capabilities are finalized, this is patched to avoid a runtime check. 473 * 474 * @num must be a compile-time constant. 475 */ 476static __always_inline bool cpus_have_const_cap(int num) 477{ 478 if (is_hyp_code()) 479 return cpus_have_final_cap(num); 480 else if (system_capabilities_finalized()) 481 return __cpus_have_const_cap(num); 482 else 483 return cpus_have_cap(num); 484} 485 486static inline void cpus_set_cap(unsigned int num) 487{ 488 if (num >= ARM64_NCAPS) { 489 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n", 490 num, ARM64_NCAPS); 491 } else { 492 __set_bit(num, cpu_hwcaps); 493 } 494} 495 496static inline int __attribute_const__ 497cpuid_feature_extract_signed_field_width(u64 features, int field, int width) 498{ 499 return (s64)(features << (64 - width - field)) >> (64 - width); 500} 501 502static inline int __attribute_const__ 503cpuid_feature_extract_signed_field(u64 features, int field) 504{ 505 return cpuid_feature_extract_signed_field_width(features, field, 4); 506} 507 508static __always_inline unsigned int __attribute_const__ 509cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width) 510{ 511 return (u64)(features << (64 - width - field)) >> (64 - width); 512} 513 514static __always_inline unsigned int __attribute_const__ 515cpuid_feature_extract_unsigned_field(u64 features, int field) 516{ 517 return cpuid_feature_extract_unsigned_field_width(features, field, 4); 518} 519 520/* 521 * Fields that identify the version of the Performance Monitors Extension do 522 * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825, 523 * "Alternative ID scheme used for the Performance Monitors Extension version". 524 */ 525static inline u64 __attribute_const__ 526cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap) 527{ 528 u64 val = cpuid_feature_extract_unsigned_field(features, field); 529 u64 mask = GENMASK_ULL(field + 3, field); 530 531 /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */ 532 if (val == 0xf) 533 val = 0; 534 535 if (val > cap) { 536 features &= ~mask; 537 features |= (cap << field) & mask; 538 } 539 540 return features; 541} 542 543static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp) 544{ 545 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift); 546} 547 548static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg) 549{ 550 return (reg->user_val | (reg->sys_val & reg->user_mask)); 551} 552 553static inline int __attribute_const__ 554cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign) 555{ 556 return (sign) ? 557 cpuid_feature_extract_signed_field_width(features, field, width) : 558 cpuid_feature_extract_unsigned_field_width(features, field, width); 559} 560 561static inline int __attribute_const__ 562cpuid_feature_extract_field(u64 features, int field, bool sign) 563{ 564 return cpuid_feature_extract_field_width(features, field, 4, sign); 565} 566 567static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val) 568{ 569 return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign); 570} 571 572static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0) 573{ 574 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 || 575 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1; 576} 577 578static inline bool id_aa64pfr0_32bit_el1(u64 pfr0) 579{ 580 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SHIFT); 581 582 return val == ID_AA64PFR0_EL1_32BIT_64BIT; 583} 584 585static inline bool id_aa64pfr0_32bit_el0(u64 pfr0) 586{ 587 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT); 588 589 return val == ID_AA64PFR0_EL0_32BIT_64BIT; 590} 591 592static inline bool id_aa64pfr0_sve(u64 pfr0) 593{ 594 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT); 595 596 return val > 0; 597} 598 599void __init setup_cpu_features(void); 600void check_local_cpu_capabilities(void); 601 602u64 read_sanitised_ftr_reg(u32 id); 603 604static inline bool cpu_supports_mixed_endian_el0(void) 605{ 606 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); 607} 608 609static inline bool supports_csv2p3(int scope) 610{ 611 u64 pfr0; 612 u8 csv2_val; 613 614 if (scope == SCOPE_LOCAL_CPU) 615 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1); 616 else 617 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 618 619 csv2_val = cpuid_feature_extract_unsigned_field(pfr0, 620 ID_AA64PFR0_CSV2_SHIFT); 621 return csv2_val == 3; 622} 623 624static inline bool supports_clearbhb(int scope) 625{ 626 u64 isar2; 627 628 if (scope == SCOPE_LOCAL_CPU) 629 isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1); 630 else 631 isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); 632 633 return cpuid_feature_extract_unsigned_field(isar2, 634 ID_AA64ISAR2_CLEARBHB_SHIFT); 635} 636 637static inline bool system_supports_32bit_el0(void) 638{ 639 return cpus_have_const_cap(ARM64_HAS_32BIT_EL0); 640} 641 642static inline bool system_supports_4kb_granule(void) 643{ 644 u64 mmfr0; 645 u32 val; 646 647 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 648 val = cpuid_feature_extract_unsigned_field(mmfr0, 649 ID_AA64MMFR0_TGRAN4_SHIFT); 650 651 return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) && 652 (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX); 653} 654 655static inline bool system_supports_64kb_granule(void) 656{ 657 u64 mmfr0; 658 u32 val; 659 660 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 661 val = cpuid_feature_extract_unsigned_field(mmfr0, 662 ID_AA64MMFR0_TGRAN64_SHIFT); 663 664 return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) && 665 (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX); 666} 667 668static inline bool system_supports_16kb_granule(void) 669{ 670 u64 mmfr0; 671 u32 val; 672 673 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 674 val = cpuid_feature_extract_unsigned_field(mmfr0, 675 ID_AA64MMFR0_TGRAN16_SHIFT); 676 677 return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) && 678 (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX); 679} 680 681static inline bool system_supports_mixed_endian_el0(void) 682{ 683 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1)); 684} 685 686static inline bool system_supports_mixed_endian(void) 687{ 688 u64 mmfr0; 689 u32 val; 690 691 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 692 val = cpuid_feature_extract_unsigned_field(mmfr0, 693 ID_AA64MMFR0_BIGENDEL_SHIFT); 694 695 return val == 0x1; 696} 697 698static __always_inline bool system_supports_fpsimd(void) 699{ 700 return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD); 701} 702 703static inline bool system_uses_ttbr0_pan(void) 704{ 705 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) && 706 !cpus_have_const_cap(ARM64_HAS_PAN); 707} 708 709static __always_inline bool system_supports_sve(void) 710{ 711 return IS_ENABLED(CONFIG_ARM64_SVE) && 712 cpus_have_const_cap(ARM64_SVE); 713} 714 715static __always_inline bool system_supports_cnp(void) 716{ 717 return IS_ENABLED(CONFIG_ARM64_CNP) && 718 cpus_have_const_cap(ARM64_HAS_CNP); 719} 720 721static inline bool system_supports_address_auth(void) 722{ 723 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) && 724 cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH); 725} 726 727static inline bool system_supports_generic_auth(void) 728{ 729 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) && 730 cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH); 731} 732 733static __always_inline bool system_uses_irq_prio_masking(void) 734{ 735 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 736 cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING); 737} 738 739static inline bool system_supports_mte(void) 740{ 741 return IS_ENABLED(CONFIG_ARM64_MTE) && 742 cpus_have_const_cap(ARM64_MTE); 743} 744 745static inline bool system_has_prio_mask_debugging(void) 746{ 747 return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) && 748 system_uses_irq_prio_masking(); 749} 750 751static inline bool system_supports_bti(void) 752{ 753 return IS_ENABLED(CONFIG_ARM64_BTI) && cpus_have_const_cap(ARM64_BTI); 754} 755 756static inline bool system_supports_tlb_range(void) 757{ 758 return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) && 759 cpus_have_const_cap(ARM64_HAS_TLB_RANGE); 760} 761 762int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); 763bool try_emulate_mrs(struct pt_regs *regs, u32 isn); 764 765static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) 766{ 767 switch (parange) { 768 case 0: return 32; 769 case 1: return 36; 770 case 2: return 40; 771 case 3: return 42; 772 case 4: return 44; 773 case 5: return 48; 774 case 6: return 52; 775 /* 776 * A future PE could use a value unknown to the kernel. 777 * However, by the "D10.1.4 Principles of the ID scheme 778 * for fields in ID registers", ARM DDI 0487C.a, any new 779 * value is guaranteed to be higher than what we know already. 780 * As a safe limit, we return the limit supported by the kernel. 781 */ 782 default: return CONFIG_ARM64_PA_BITS; 783 } 784} 785 786/* Check whether hardware update of the Access flag is supported */ 787static inline bool cpu_has_hw_af(void) 788{ 789 u64 mmfr1; 790 791 if (!IS_ENABLED(CONFIG_ARM64_HW_AFDBM)) 792 return false; 793 794 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 795 return cpuid_feature_extract_unsigned_field(mmfr1, 796 ID_AA64MMFR1_HADBS_SHIFT); 797} 798 799#ifdef CONFIG_ARM64_AMU_EXTN 800/* Check whether the cpu supports the Activity Monitors Unit (AMU) */ 801extern bool cpu_has_amu_feat(int cpu); 802#endif 803 804static inline unsigned int get_vmid_bits(u64 mmfr1) 805{ 806 int vmid_bits; 807 808 vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1, 809 ID_AA64MMFR1_VMIDBITS_SHIFT); 810 if (vmid_bits == ID_AA64MMFR1_VMIDBITS_16) 811 return 16; 812 813 /* 814 * Return the default here even if any reserved 815 * value is fetched from the system register. 816 */ 817 return 8; 818} 819 820u32 get_kvm_ipa_limit(void); 821void dump_cpu_features(void); 822 823#endif /* __ASSEMBLY__ */ 824 825#endif 826