1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5#ifndef __ASM_CACHE_H
6#define __ASM_CACHE_H
7
8#include <asm/cputype.h>
9
10#define CTR_L1IP_SHIFT		14
11#define CTR_L1IP_MASK		3
12#define CTR_DMINLINE_SHIFT	16
13#define CTR_IMINLINE_SHIFT	0
14#define CTR_IMINLINE_MASK	0xf
15#define CTR_ERG_SHIFT		20
16#define CTR_CWG_SHIFT		24
17#define CTR_CWG_MASK		15
18#define CTR_IDC_SHIFT		28
19#define CTR_DIC_SHIFT		29
20
21#define CTR_CACHE_MINLINE_MASK	\
22	(0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
23
24#define CTR_L1IP(ctr)		(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
25
26#define ICACHE_POLICY_VPIPT	0
27#define ICACHE_POLICY_RESERVED	1
28#define ICACHE_POLICY_VIPT	2
29#define ICACHE_POLICY_PIPT	3
30
31#define L1_CACHE_SHIFT		(6)
32#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
33
34
35#define CLIDR_LOUU_SHIFT	27
36#define CLIDR_LOC_SHIFT		24
37#define CLIDR_LOUIS_SHIFT	21
38
39#define CLIDR_LOUU(clidr)	(((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
40#define CLIDR_LOC(clidr)	(((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
41#define CLIDR_LOUIS(clidr)	(((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
42
43/*
44 * Memory returned by kmalloc() may be used for DMA, so we must make
45 * sure that all such allocations are cache aligned. Otherwise,
46 * unrelated code may cause parts of the buffer to be read into the
47 * cache before the transfer is done, causing old data to be seen by
48 * the CPU.
49 */
50#define ARCH_DMA_MINALIGN	(128)
51
52#ifdef CONFIG_KASAN_SW_TAGS
53#define ARCH_SLAB_MINALIGN	(1ULL << KASAN_SHADOW_SCALE_SHIFT)
54#endif
55
56#ifndef __ASSEMBLY__
57
58#include <linux/bitops.h>
59
60#define ICACHEF_ALIASING	0
61#define ICACHEF_VPIPT		1
62extern unsigned long __icache_flags;
63
64/*
65 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
66 * permitted in the I-cache.
67 */
68static inline int icache_is_aliasing(void)
69{
70	return test_bit(ICACHEF_ALIASING, &__icache_flags);
71}
72
73static __always_inline int icache_is_vpipt(void)
74{
75	return test_bit(ICACHEF_VPIPT, &__icache_flags);
76}
77
78static inline u32 cache_type_cwg(void)
79{
80	return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
81}
82
83#define __read_mostly __section(".data..read_mostly")
84
85static inline int cache_line_size_of_cpu(void)
86{
87	u32 cwg = cache_type_cwg();
88
89	return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
90}
91
92int cache_line_size(void);
93
94/*
95 * Read the effective value of CTR_EL0.
96 *
97 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
98 * section D10.2.33 "CTR_EL0, Cache Type Register" :
99 *
100 * CTR_EL0.IDC reports the data cache clean requirements for
101 * instruction to data coherence.
102 *
103 *  0 - dcache clean to PoU is required unless :
104 *     (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
105 *  1 - dcache clean to PoU is not required for i-to-d coherence.
106 *
107 * This routine provides the CTR_EL0 with the IDC field updated to the
108 * effective state.
109 */
110static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
111{
112	u32 ctr = read_cpuid_cachetype();
113
114	if (!(ctr & BIT(CTR_IDC_SHIFT))) {
115		u64 clidr = read_sysreg(clidr_el1);
116
117		if (CLIDR_LOC(clidr) == 0 ||
118		    (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
119			ctr |= BIT(CTR_IDC_SHIFT);
120	}
121
122	return ctr;
123}
124
125#endif	/* __ASSEMBLY__ */
126
127#endif
128