18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * ARM Ltd. 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * ARMv8 Foundation model DTS (spin table configuration) 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci&cpu0 { 88c2ecf20Sopenharmony_ci enable-method = "spin-table"; 98c2ecf20Sopenharmony_ci cpu-release-addr = <0x0 0x8000fff8>; 108c2ecf20Sopenharmony_ci}; 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci&cpu1 { 138c2ecf20Sopenharmony_ci enable-method = "spin-table"; 148c2ecf20Sopenharmony_ci cpu-release-addr = <0x0 0x8000fff8>; 158c2ecf20Sopenharmony_ci}; 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci&cpu2 { 188c2ecf20Sopenharmony_ci enable-method = "spin-table"; 198c2ecf20Sopenharmony_ci cpu-release-addr = <0x0 0x8000fff8>; 208c2ecf20Sopenharmony_ci}; 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci&cpu3 { 238c2ecf20Sopenharmony_ci enable-method = "spin-table"; 248c2ecf20Sopenharmony_ci cpu-release-addr = <0x0 0x8000fff8>; 258c2ecf20Sopenharmony_ci}; 26