18c2ecf20Sopenharmony_ci/*
28c2ecf20Sopenharmony_ci * ARM Ltd.
38c2ecf20Sopenharmony_ci *
48c2ecf20Sopenharmony_ci * ARMv8 Foundation model DTS (GICv2 configuration)
58c2ecf20Sopenharmony_ci */
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci/ {
88c2ecf20Sopenharmony_ci	gic: interrupt-controller@2c001000 {
98c2ecf20Sopenharmony_ci		compatible = "arm,gic-400", "arm,cortex-a15-gic";
108c2ecf20Sopenharmony_ci		#interrupt-cells = <3>;
118c2ecf20Sopenharmony_ci		#address-cells = <1>;
128c2ecf20Sopenharmony_ci		interrupt-controller;
138c2ecf20Sopenharmony_ci		reg = <0x0 0x2c001000 0 0x1000>,
148c2ecf20Sopenharmony_ci		      <0x0 0x2c002000 0 0x2000>,
158c2ecf20Sopenharmony_ci		      <0x0 0x2c004000 0 0x2000>,
168c2ecf20Sopenharmony_ci		      <0x0 0x2c006000 0 0x2000>;
178c2ecf20Sopenharmony_ci		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
188c2ecf20Sopenharmony_ci	};
198c2ecf20Sopenharmony_ci};
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