18c2ecf20Sopenharmony_ci/*
28c2ecf20Sopenharmony_ci * arch/arm/plat-orion/irq.c
38c2ecf20Sopenharmony_ci *
48c2ecf20Sopenharmony_ci * Marvell Orion SoC IRQ handling.
58c2ecf20Sopenharmony_ci *
68c2ecf20Sopenharmony_ci * This file is licensed under the terms of the GNU General Public
78c2ecf20Sopenharmony_ci * License version 2.  This program is licensed "as is" without any
88c2ecf20Sopenharmony_ci * warranty of any kind, whether express or implied.
98c2ecf20Sopenharmony_ci */
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci#include <linux/kernel.h>
128c2ecf20Sopenharmony_ci#include <linux/init.h>
138c2ecf20Sopenharmony_ci#include <linux/irq.h>
148c2ecf20Sopenharmony_ci#include <linux/irqdomain.h>
158c2ecf20Sopenharmony_ci#include <linux/io.h>
168c2ecf20Sopenharmony_ci#include <linux/of_address.h>
178c2ecf20Sopenharmony_ci#include <linux/of_irq.h>
188c2ecf20Sopenharmony_ci#include <asm/exception.h>
198c2ecf20Sopenharmony_ci#include <plat/irq.h>
208c2ecf20Sopenharmony_ci#include <plat/orion-gpio.h>
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_civoid __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
238c2ecf20Sopenharmony_ci{
248c2ecf20Sopenharmony_ci	struct irq_chip_generic *gc;
258c2ecf20Sopenharmony_ci	struct irq_chip_type *ct;
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci	/*
288c2ecf20Sopenharmony_ci	 * Mask all interrupts initially.
298c2ecf20Sopenharmony_ci	 */
308c2ecf20Sopenharmony_ci	writel(0, maskaddr);
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci	gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
338c2ecf20Sopenharmony_ci				    handle_level_irq);
348c2ecf20Sopenharmony_ci	ct = gc->chip_types;
358c2ecf20Sopenharmony_ci	ct->chip.irq_mask = irq_gc_mask_clr_bit;
368c2ecf20Sopenharmony_ci	ct->chip.irq_unmask = irq_gc_mask_set_bit;
378c2ecf20Sopenharmony_ci	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
388c2ecf20Sopenharmony_ci			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
398c2ecf20Sopenharmony_ci}
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