18c2ecf20Sopenharmony_ci/*
28c2ecf20Sopenharmony_ci * arch/arm/plat-orion/include/plat/pcie.h
38c2ecf20Sopenharmony_ci *
48c2ecf20Sopenharmony_ci * Marvell Orion SoC PCIe handling.
58c2ecf20Sopenharmony_ci *
68c2ecf20Sopenharmony_ci * This file is licensed under the terms of the GNU General Public
78c2ecf20Sopenharmony_ci * License version 2.  This program is licensed "as is" without any
88c2ecf20Sopenharmony_ci * warranty of any kind, whether express or implied.
98c2ecf20Sopenharmony_ci */
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci#ifndef __PLAT_PCIE_H
128c2ecf20Sopenharmony_ci#define __PLAT_PCIE_H
138c2ecf20Sopenharmony_ci
148c2ecf20Sopenharmony_cistruct pci_bus;
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ciu32 orion_pcie_dev_id(void __iomem *base);
178c2ecf20Sopenharmony_ciu32 orion_pcie_rev(void __iomem *base);
188c2ecf20Sopenharmony_ciint orion_pcie_link_up(void __iomem *base);
198c2ecf20Sopenharmony_ciint orion_pcie_x4_mode(void __iomem *base);
208c2ecf20Sopenharmony_ciint orion_pcie_get_local_bus_nr(void __iomem *base);
218c2ecf20Sopenharmony_civoid orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
228c2ecf20Sopenharmony_civoid orion_pcie_reset(void __iomem *base);
238c2ecf20Sopenharmony_civoid orion_pcie_setup(void __iomem *base);
248c2ecf20Sopenharmony_ciint orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
258c2ecf20Sopenharmony_ci		       u32 devfn, int where, int size, u32 *val);
268c2ecf20Sopenharmony_ciint orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
278c2ecf20Sopenharmony_ci			   u32 devfn, int where, int size, u32 *val);
288c2ecf20Sopenharmony_ciint orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
298c2ecf20Sopenharmony_ci			  u32 devfn, int where, int size, u32 *val);
308c2ecf20Sopenharmony_ciint orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
318c2ecf20Sopenharmony_ci		       u32 devfn, int where, int size, u32 val);
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_ci#endif
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