1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/arch/arm/mm/mmu.c 4 * 5 * Copyright (C) 1995-2005 Russell King 6 */ 7#include <linux/module.h> 8#include <linux/kernel.h> 9#include <linux/errno.h> 10#include <linux/init.h> 11#include <linux/mman.h> 12#include <linux/nodemask.h> 13#include <linux/memblock.h> 14#include <linux/fs.h> 15#include <linux/vmalloc.h> 16#include <linux/sizes.h> 17 18#include <asm/cp15.h> 19#include <asm/cputype.h> 20#include <asm/cachetype.h> 21#include <asm/fixmap.h> 22#include <asm/sections.h> 23#include <asm/setup.h> 24#include <asm/smp_plat.h> 25#include <asm/tlb.h> 26#include <asm/highmem.h> 27#include <asm/system_info.h> 28#include <asm/traps.h> 29#include <asm/procinfo.h> 30#include <asm/memory.h> 31#include <asm/pgalloc.h> 32#include <asm/kasan_def.h> 33 34#include <asm/mach/arch.h> 35#include <asm/mach/map.h> 36#include <asm/mach/pci.h> 37#include <asm/fixmap.h> 38 39#include "fault.h" 40#include "mm.h" 41#include "tcm.h" 42 43extern unsigned long __atags_pointer; 44 45/* 46 * empty_zero_page is a special page that is used for 47 * zero-initialized data and COW. 48 */ 49struct page *empty_zero_page; 50EXPORT_SYMBOL(empty_zero_page); 51 52/* 53 * The pmd table for the upper-most set of pages. 54 */ 55pmd_t *top_pmd; 56 57pmdval_t user_pmd_table = _PAGE_USER_TABLE; 58 59#define CPOLICY_UNCACHED 0 60#define CPOLICY_BUFFERED 1 61#define CPOLICY_WRITETHROUGH 2 62#define CPOLICY_WRITEBACK 3 63#define CPOLICY_WRITEALLOC 4 64 65static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 66static unsigned int ecc_mask __initdata = 0; 67pgprot_t pgprot_user; 68pgprot_t pgprot_kernel; 69 70EXPORT_SYMBOL(pgprot_user); 71EXPORT_SYMBOL(pgprot_kernel); 72 73struct cachepolicy { 74 const char policy[16]; 75 unsigned int cr_mask; 76 pmdval_t pmd; 77 pteval_t pte; 78}; 79 80static struct cachepolicy cache_policies[] __initdata = { 81 { 82 .policy = "uncached", 83 .cr_mask = CR_W|CR_C, 84 .pmd = PMD_SECT_UNCACHED, 85 .pte = L_PTE_MT_UNCACHED, 86 }, { 87 .policy = "buffered", 88 .cr_mask = CR_C, 89 .pmd = PMD_SECT_BUFFERED, 90 .pte = L_PTE_MT_BUFFERABLE, 91 }, { 92 .policy = "writethrough", 93 .cr_mask = 0, 94 .pmd = PMD_SECT_WT, 95 .pte = L_PTE_MT_WRITETHROUGH, 96 }, { 97 .policy = "writeback", 98 .cr_mask = 0, 99 .pmd = PMD_SECT_WB, 100 .pte = L_PTE_MT_WRITEBACK, 101 }, { 102 .policy = "writealloc", 103 .cr_mask = 0, 104 .pmd = PMD_SECT_WBWA, 105 .pte = L_PTE_MT_WRITEALLOC, 106 } 107}; 108 109#ifdef CONFIG_CPU_CP15 110static unsigned long initial_pmd_value __initdata = 0; 111 112/* 113 * Initialise the cache_policy variable with the initial state specified 114 * via the "pmd" value. This is used to ensure that on ARMv6 and later, 115 * the C code sets the page tables up with the same policy as the head 116 * assembly code, which avoids an illegal state where the TLBs can get 117 * confused. See comments in early_cachepolicy() for more information. 118 */ 119void __init init_default_cache_policy(unsigned long pmd) 120{ 121 int i; 122 123 initial_pmd_value = pmd; 124 125 pmd &= PMD_SECT_CACHE_MASK; 126 127 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) 128 if (cache_policies[i].pmd == pmd) { 129 cachepolicy = i; 130 break; 131 } 132 133 if (i == ARRAY_SIZE(cache_policies)) 134 pr_err("ERROR: could not find cache policy\n"); 135} 136 137/* 138 * These are useful for identifying cache coherency problems by allowing 139 * the cache or the cache and writebuffer to be turned off. (Note: the 140 * write buffer should not be on and the cache off). 141 */ 142static int __init early_cachepolicy(char *p) 143{ 144 int i, selected = -1; 145 146 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 147 int len = strlen(cache_policies[i].policy); 148 149 if (memcmp(p, cache_policies[i].policy, len) == 0) { 150 selected = i; 151 break; 152 } 153 } 154 155 if (selected == -1) 156 pr_err("ERROR: unknown or unsupported cache policy\n"); 157 158 /* 159 * This restriction is partly to do with the way we boot; it is 160 * unpredictable to have memory mapped using two different sets of 161 * memory attributes (shared, type, and cache attribs). We can not 162 * change these attributes once the initial assembly has setup the 163 * page tables. 164 */ 165 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) { 166 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n", 167 cache_policies[cachepolicy].policy); 168 return 0; 169 } 170 171 if (selected != cachepolicy) { 172 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask); 173 cachepolicy = selected; 174 flush_cache_all(); 175 set_cr(cr); 176 } 177 return 0; 178} 179early_param("cachepolicy", early_cachepolicy); 180 181static int __init early_nocache(char *__unused) 182{ 183 char *p = "buffered"; 184 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p); 185 early_cachepolicy(p); 186 return 0; 187} 188early_param("nocache", early_nocache); 189 190static int __init early_nowrite(char *__unused) 191{ 192 char *p = "uncached"; 193 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p); 194 early_cachepolicy(p); 195 return 0; 196} 197early_param("nowb", early_nowrite); 198 199#ifndef CONFIG_ARM_LPAE 200static int __init early_ecc(char *p) 201{ 202 if (memcmp(p, "on", 2) == 0) 203 ecc_mask = PMD_PROTECTION; 204 else if (memcmp(p, "off", 3) == 0) 205 ecc_mask = 0; 206 return 0; 207} 208early_param("ecc", early_ecc); 209#endif 210 211#else /* ifdef CONFIG_CPU_CP15 */ 212 213static int __init early_cachepolicy(char *p) 214{ 215 pr_warn("cachepolicy kernel parameter not supported without cp15\n"); 216 return 0; 217} 218early_param("cachepolicy", early_cachepolicy); 219 220static int __init noalign_setup(char *__unused) 221{ 222 pr_warn("noalign kernel parameter not supported without cp15\n"); 223 return 1; 224} 225__setup("noalign", noalign_setup); 226 227#endif /* ifdef CONFIG_CPU_CP15 / else */ 228 229#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN 230#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE 231#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE 232 233static struct mem_type mem_types[] __ro_after_init = { 234 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 235 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | 236 L_PTE_SHARED, 237 .prot_l1 = PMD_TYPE_TABLE, 238 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, 239 .domain = DOMAIN_IO, 240 }, 241 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 242 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, 243 .prot_l1 = PMD_TYPE_TABLE, 244 .prot_sect = PROT_SECT_DEVICE, 245 .domain = DOMAIN_IO, 246 }, 247 [MT_DEVICE_CACHED] = { /* ioremap_cache */ 248 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, 249 .prot_l1 = PMD_TYPE_TABLE, 250 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 251 .domain = DOMAIN_IO, 252 }, 253 [MT_DEVICE_WC] = { /* ioremap_wc */ 254 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 255 .prot_l1 = PMD_TYPE_TABLE, 256 .prot_sect = PROT_SECT_DEVICE, 257 .domain = DOMAIN_IO, 258 }, 259 [MT_UNCACHED] = { 260 .prot_pte = PROT_PTE_DEVICE, 261 .prot_l1 = PMD_TYPE_TABLE, 262 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 263 .domain = DOMAIN_IO, 264 }, 265 [MT_CACHECLEAN] = { 266 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 267 .domain = DOMAIN_KERNEL, 268 }, 269#ifndef CONFIG_ARM_LPAE 270 [MT_MINICLEAN] = { 271 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, 272 .domain = DOMAIN_KERNEL, 273 }, 274#endif 275 [MT_LOW_VECTORS] = { 276 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 277 L_PTE_RDONLY, 278 .prot_l1 = PMD_TYPE_TABLE, 279 .domain = DOMAIN_VECTORS, 280 }, 281 [MT_HIGH_VECTORS] = { 282 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 283 L_PTE_USER | L_PTE_RDONLY, 284 .prot_l1 = PMD_TYPE_TABLE, 285 .domain = DOMAIN_VECTORS, 286 }, 287 [MT_MEMORY_RWX] = { 288 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 289 .prot_l1 = PMD_TYPE_TABLE, 290 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 291 .domain = DOMAIN_KERNEL, 292 }, 293 [MT_MEMORY_RW] = { 294 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 295 L_PTE_XN, 296 .prot_l1 = PMD_TYPE_TABLE, 297 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 298 .domain = DOMAIN_KERNEL, 299 }, 300 [MT_MEMORY_RO] = { 301 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 302 L_PTE_XN | L_PTE_RDONLY, 303 .prot_l1 = PMD_TYPE_TABLE, 304#ifdef CONFIG_ARM_LPAE 305 .prot_sect = PMD_TYPE_SECT | L_PMD_SECT_RDONLY | PMD_SECT_AP2, 306#else 307 .prot_sect = PMD_TYPE_SECT, 308#endif 309 .domain = DOMAIN_KERNEL, 310 }, 311 [MT_ROM] = { 312 .prot_sect = PMD_TYPE_SECT, 313 .domain = DOMAIN_KERNEL, 314 }, 315 [MT_MEMORY_RWX_NONCACHED] = { 316 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 317 L_PTE_MT_BUFFERABLE, 318 .prot_l1 = PMD_TYPE_TABLE, 319 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 320 .domain = DOMAIN_KERNEL, 321 }, 322 [MT_MEMORY_RW_DTCM] = { 323 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 324 L_PTE_XN, 325 .prot_l1 = PMD_TYPE_TABLE, 326 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 327 .domain = DOMAIN_KERNEL, 328 }, 329 [MT_MEMORY_RWX_ITCM] = { 330 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 331 .prot_l1 = PMD_TYPE_TABLE, 332 .domain = DOMAIN_KERNEL, 333 }, 334 [MT_MEMORY_RW_SO] = { 335 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 336 L_PTE_MT_UNCACHED | L_PTE_XN, 337 .prot_l1 = PMD_TYPE_TABLE, 338 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | 339 PMD_SECT_UNCACHED | PMD_SECT_XN, 340 .domain = DOMAIN_KERNEL, 341 }, 342 [MT_MEMORY_DMA_READY] = { 343 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 344 L_PTE_XN, 345 .prot_l1 = PMD_TYPE_TABLE, 346 .domain = DOMAIN_KERNEL, 347 }, 348}; 349 350const struct mem_type *get_mem_type(unsigned int type) 351{ 352 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 353} 354EXPORT_SYMBOL(get_mem_type); 355 356static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr); 357 358static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS] 359 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata; 360 361static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr) 362{ 363 return &bm_pte[pte_index(addr)]; 364} 365 366static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr) 367{ 368 return pte_offset_kernel(dir, addr); 369} 370 371static inline pmd_t * __init fixmap_pmd(unsigned long addr) 372{ 373 return pmd_off_k(addr); 374} 375 376void __init early_fixmap_init(void) 377{ 378 pmd_t *pmd; 379 380 /* 381 * The early fixmap range spans multiple pmds, for which 382 * we are not prepared: 383 */ 384 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT) 385 != FIXADDR_TOP >> PMD_SHIFT); 386 387 pmd = fixmap_pmd(FIXADDR_TOP); 388 pmd_populate_kernel(&init_mm, pmd, bm_pte); 389 390 pte_offset_fixmap = pte_offset_early_fixmap; 391} 392 393/* 394 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range(). 395 * As a result, this can only be called with preemption disabled, as under 396 * stop_machine(). 397 */ 398void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) 399{ 400 unsigned long vaddr = __fix_to_virt(idx); 401 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr); 402 403 /* Make sure fixmap region does not exceed available allocation. */ 404 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) > 405 FIXADDR_END); 406 BUG_ON(idx >= __end_of_fixed_addresses); 407 408 /* We support only device mappings before pgprot_kernel is set. */ 409 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) && 410 pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0)) 411 return; 412 413 if (pgprot_val(prot)) 414 set_pte_at(NULL, vaddr, pte, 415 pfn_pte(phys >> PAGE_SHIFT, prot)); 416 else 417 pte_clear(NULL, vaddr, pte); 418 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); 419} 420 421/* 422 * Adjust the PMD section entries according to the CPU in use. 423 */ 424static void __init build_mem_type_table(void) 425{ 426 struct cachepolicy *cp; 427 unsigned int cr = get_cr(); 428 pteval_t user_pgprot, kern_pgprot, vecs_pgprot; 429 int cpu_arch = cpu_architecture(); 430 int i; 431 432 if (cpu_arch < CPU_ARCH_ARMv6) { 433#if defined(CONFIG_CPU_DCACHE_DISABLE) 434 if (cachepolicy > CPOLICY_BUFFERED) 435 cachepolicy = CPOLICY_BUFFERED; 436#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 437 if (cachepolicy > CPOLICY_WRITETHROUGH) 438 cachepolicy = CPOLICY_WRITETHROUGH; 439#endif 440 } 441 if (cpu_arch < CPU_ARCH_ARMv5) { 442 if (cachepolicy >= CPOLICY_WRITEALLOC) 443 cachepolicy = CPOLICY_WRITEBACK; 444 ecc_mask = 0; 445 } 446 447 if (is_smp()) { 448 if (cachepolicy != CPOLICY_WRITEALLOC) { 449 pr_warn("Forcing write-allocate cache policy for SMP\n"); 450 cachepolicy = CPOLICY_WRITEALLOC; 451 } 452 if (!(initial_pmd_value & PMD_SECT_S)) { 453 pr_warn("Forcing shared mappings for SMP\n"); 454 initial_pmd_value |= PMD_SECT_S; 455 } 456 } 457 458 /* 459 * Strip out features not present on earlier architectures. 460 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those 461 * without extended page tables don't have the 'Shared' bit. 462 */ 463 if (cpu_arch < CPU_ARCH_ARMv5) 464 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 465 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); 466 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) 467 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 468 mem_types[i].prot_sect &= ~PMD_SECT_S; 469 470 /* 471 * ARMv5 and lower, bit 4 must be set for page tables (was: cache 472 * "update-able on write" bit on ARM610). However, Xscale and 473 * Xscale3 require this bit to be cleared. 474 */ 475 if (cpu_is_xscale_family()) { 476 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 477 mem_types[i].prot_sect &= ~PMD_BIT4; 478 mem_types[i].prot_l1 &= ~PMD_BIT4; 479 } 480 } else if (cpu_arch < CPU_ARCH_ARMv6) { 481 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 482 if (mem_types[i].prot_l1) 483 mem_types[i].prot_l1 |= PMD_BIT4; 484 if (mem_types[i].prot_sect) 485 mem_types[i].prot_sect |= PMD_BIT4; 486 } 487 } 488 489 /* 490 * Mark the device areas according to the CPU/architecture. 491 */ 492 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { 493 if (!cpu_is_xsc3()) { 494 /* 495 * Mark device regions on ARMv6+ as execute-never 496 * to prevent speculative instruction fetches. 497 */ 498 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; 499 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; 500 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; 501 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; 502 503 /* Also setup NX memory mapping */ 504 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; 505 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_XN; 506 } 507 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 508 /* 509 * For ARMv7 with TEX remapping, 510 * - shared device is SXCB=1100 511 * - nonshared device is SXCB=0100 512 * - write combine device mem is SXCB=0001 513 * (Uncached Normal memory) 514 */ 515 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); 516 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); 517 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 518 } else if (cpu_is_xsc3()) { 519 /* 520 * For Xscale3, 521 * - shared device is TEXCB=00101 522 * - nonshared device is TEXCB=01000 523 * - write combine device mem is TEXCB=00100 524 * (Inner/Outer Uncacheable in xsc3 parlance) 525 */ 526 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; 527 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 528 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 529 } else { 530 /* 531 * For ARMv6 and ARMv7 without TEX remapping, 532 * - shared device is TEXCB=00001 533 * - nonshared device is TEXCB=01000 534 * - write combine device mem is TEXCB=00100 535 * (Uncached Normal in ARMv6 parlance). 536 */ 537 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 538 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 539 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 540 } 541 } else { 542 /* 543 * On others, write combining is "Uncached/Buffered" 544 */ 545 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 546 } 547 548 /* 549 * Now deal with the memory-type mappings 550 */ 551 cp = &cache_policies[cachepolicy]; 552 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; 553 554#ifndef CONFIG_ARM_LPAE 555 /* 556 * We don't use domains on ARMv6 (since this causes problems with 557 * v6/v7 kernels), so we must use a separate memory type for user 558 * r/o, kernel r/w to map the vectors page. 559 */ 560 if (cpu_arch == CPU_ARCH_ARMv6) 561 vecs_pgprot |= L_PTE_MT_VECTORS; 562 563 /* 564 * Check is it with support for the PXN bit 565 * in the Short-descriptor translation table format descriptors. 566 */ 567 if (cpu_arch == CPU_ARCH_ARMv7 && 568 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) { 569 user_pmd_table |= PMD_PXNTABLE; 570 } 571#endif 572 573 /* 574 * ARMv6 and above have extended page tables. 575 */ 576 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 577#ifndef CONFIG_ARM_LPAE 578 /* 579 * Mark cache clean areas and XIP ROM read only 580 * from SVC mode and no access from userspace. 581 */ 582 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 583 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 584 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 585 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 586#endif 587 588 /* 589 * If the initial page tables were created with the S bit 590 * set, then we need to do the same here for the same 591 * reasons given in early_cachepolicy(). 592 */ 593 if (initial_pmd_value & PMD_SECT_S) { 594 user_pgprot |= L_PTE_SHARED; 595 kern_pgprot |= L_PTE_SHARED; 596 vecs_pgprot |= L_PTE_SHARED; 597 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; 598 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; 599 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 600 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 601 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; 602 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; 603 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; 604 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; 605 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_S; 606 mem_types[MT_MEMORY_RO].prot_pte |= L_PTE_SHARED; 607 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; 608 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; 609 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; 610 } 611 } 612 613 /* 614 * Non-cacheable Normal - intended for memory areas that must 615 * not cause dirty cache line writebacks when used 616 */ 617 if (cpu_arch >= CPU_ARCH_ARMv6) { 618 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 619 /* Non-cacheable Normal is XCB = 001 */ 620 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= 621 PMD_SECT_BUFFERED; 622 } else { 623 /* For both ARMv6 and non-TEX-remapping ARMv7 */ 624 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= 625 PMD_SECT_TEX(1); 626 } 627 } else { 628 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; 629 } 630 631#ifdef CONFIG_ARM_LPAE 632 /* 633 * Do not generate access flag faults for the kernel mappings. 634 */ 635 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 636 mem_types[i].prot_pte |= PTE_EXT_AF; 637 if (mem_types[i].prot_sect) 638 mem_types[i].prot_sect |= PMD_SECT_AF; 639 } 640 kern_pgprot |= PTE_EXT_AF; 641 vecs_pgprot |= PTE_EXT_AF; 642 643 /* 644 * Set PXN for user mappings 645 */ 646 user_pgprot |= PTE_EXT_PXN; 647#endif 648 649 for (i = 0; i < 16; i++) { 650 pteval_t v = pgprot_val(protection_map[i]); 651 protection_map[i] = __pgprot(v | user_pgprot); 652 } 653 654 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; 655 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; 656 657 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 658 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 659 L_PTE_DIRTY | kern_pgprot); 660 661 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 662 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 663 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; 664 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; 665 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; 666 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; 667 mem_types[MT_MEMORY_RO].prot_sect |= ecc_mask | cp->pmd; 668 mem_types[MT_MEMORY_RO].prot_pte |= kern_pgprot; 669 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; 670 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; 671 mem_types[MT_ROM].prot_sect |= cp->pmd; 672 673 switch (cp->pmd) { 674 case PMD_SECT_WT: 675 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 676 break; 677 case PMD_SECT_WB: 678 case PMD_SECT_WBWA: 679 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 680 break; 681 } 682 pr_info("Memory policy: %sData cache %s\n", 683 ecc_mask ? "ECC enabled, " : "", cp->policy); 684 685 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 686 struct mem_type *t = &mem_types[i]; 687 if (t->prot_l1) 688 t->prot_l1 |= PMD_DOMAIN(t->domain); 689 if (t->prot_sect) 690 t->prot_sect |= PMD_DOMAIN(t->domain); 691 } 692} 693 694#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 695pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 696 unsigned long size, pgprot_t vma_prot) 697{ 698 if (!pfn_valid(pfn)) 699 return pgprot_noncached(vma_prot); 700 else if (file->f_flags & O_SYNC) 701 return pgprot_writecombine(vma_prot); 702 return vma_prot; 703} 704EXPORT_SYMBOL(phys_mem_access_prot); 705#endif 706 707#define vectors_base() (vectors_high() ? 0xffff0000 : 0) 708 709static void __init *early_alloc(unsigned long sz) 710{ 711 void *ptr = memblock_alloc(sz, sz); 712 713 if (!ptr) 714 panic("%s: Failed to allocate %lu bytes align=0x%lx\n", 715 __func__, sz, sz); 716 717 return ptr; 718} 719 720static void *__init late_alloc(unsigned long sz) 721{ 722 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz)); 723 724 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr))) 725 BUG(); 726 return ptr; 727} 728 729static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr, 730 unsigned long prot, 731 void *(*alloc)(unsigned long sz)) 732{ 733 if (pmd_none(*pmd)) { 734 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); 735 __pmd_populate(pmd, __pa(pte), prot); 736 } 737 BUG_ON(pmd_bad(*pmd)); 738 return pte_offset_kernel(pmd, addr); 739} 740 741static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, 742 unsigned long prot) 743{ 744 return arm_pte_alloc(pmd, addr, prot, early_alloc); 745} 746 747static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 748 unsigned long end, unsigned long pfn, 749 const struct mem_type *type, 750 void *(*alloc)(unsigned long sz), 751 bool ng) 752{ 753 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc); 754 do { 755 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 756 ng ? PTE_EXT_NG : 0); 757 pfn++; 758 } while (pte++, addr += PAGE_SIZE, addr != end); 759} 760 761static void __init __map_init_section(pmd_t *pmd, unsigned long addr, 762 unsigned long end, phys_addr_t phys, 763 const struct mem_type *type, bool ng) 764{ 765 pmd_t *p = pmd; 766 767#ifndef CONFIG_ARM_LPAE 768 /* 769 * In classic MMU format, puds and pmds are folded in to 770 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a 771 * group of L1 entries making up one logical pointer to 772 * an L2 table (2MB), where as PMDs refer to the individual 773 * L1 entries (1MB). Hence increment to get the correct 774 * offset for odd 1MB sections. 775 * (See arch/arm/include/asm/pgtable-2level.h) 776 */ 777 if (addr & SECTION_SIZE) 778 pmd++; 779#endif 780 do { 781 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0)); 782 phys += SECTION_SIZE; 783 } while (pmd++, addr += SECTION_SIZE, addr != end); 784 785 flush_pmd_entry(p); 786} 787 788static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, 789 unsigned long end, phys_addr_t phys, 790 const struct mem_type *type, 791 void *(*alloc)(unsigned long sz), bool ng) 792{ 793 pmd_t *pmd = pmd_offset(pud, addr); 794 unsigned long next; 795 796 do { 797 /* 798 * With LPAE, we must loop over to map 799 * all the pmds for the given range. 800 */ 801 next = pmd_addr_end(addr, end); 802 803 /* 804 * Try a section mapping - addr, next and phys must all be 805 * aligned to a section boundary. 806 */ 807 if (type->prot_sect && 808 ((addr | next | phys) & ~SECTION_MASK) == 0) { 809 __map_init_section(pmd, addr, next, phys, type, ng); 810 } else { 811 alloc_init_pte(pmd, addr, next, 812 __phys_to_pfn(phys), type, alloc, ng); 813 } 814 815 phys += next - addr; 816 817 } while (pmd++, addr = next, addr != end); 818} 819 820static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr, 821 unsigned long end, phys_addr_t phys, 822 const struct mem_type *type, 823 void *(*alloc)(unsigned long sz), bool ng) 824{ 825 pud_t *pud = pud_offset(p4d, addr); 826 unsigned long next; 827 828 do { 829 next = pud_addr_end(addr, end); 830 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng); 831 phys += next - addr; 832 } while (pud++, addr = next, addr != end); 833} 834 835static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr, 836 unsigned long end, phys_addr_t phys, 837 const struct mem_type *type, 838 void *(*alloc)(unsigned long sz), bool ng) 839{ 840 p4d_t *p4d = p4d_offset(pgd, addr); 841 unsigned long next; 842 843 do { 844 next = p4d_addr_end(addr, end); 845 alloc_init_pud(p4d, addr, next, phys, type, alloc, ng); 846 phys += next - addr; 847 } while (p4d++, addr = next, addr != end); 848} 849 850#ifndef CONFIG_ARM_LPAE 851static void __init create_36bit_mapping(struct mm_struct *mm, 852 struct map_desc *md, 853 const struct mem_type *type, 854 bool ng) 855{ 856 unsigned long addr, length, end; 857 phys_addr_t phys; 858 pgd_t *pgd; 859 860 addr = md->virtual; 861 phys = __pfn_to_phys(md->pfn); 862 length = PAGE_ALIGN(md->length); 863 864 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { 865 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n", 866 (long long)__pfn_to_phys((u64)md->pfn), addr); 867 return; 868 } 869 870 /* N.B. ARMv6 supersections are only defined to work with domain 0. 871 * Since domain assignments can in fact be arbitrary, the 872 * 'domain == 0' check below is required to insure that ARMv6 873 * supersections are only allocated for domain 0 regardless 874 * of the actual domain assignments in use. 875 */ 876 if (type->domain) { 877 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n", 878 (long long)__pfn_to_phys((u64)md->pfn), addr); 879 return; 880 } 881 882 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { 883 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n", 884 (long long)__pfn_to_phys((u64)md->pfn), addr); 885 return; 886 } 887 888 /* 889 * Shift bits [35:32] of address into bits [23:20] of PMD 890 * (See ARMv6 spec). 891 */ 892 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 893 894 pgd = pgd_offset(mm, addr); 895 end = addr + length; 896 do { 897 p4d_t *p4d = p4d_offset(pgd, addr); 898 pud_t *pud = pud_offset(p4d, addr); 899 pmd_t *pmd = pmd_offset(pud, addr); 900 int i; 901 902 for (i = 0; i < 16; i++) 903 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER | 904 (ng ? PMD_SECT_nG : 0)); 905 906 addr += SUPERSECTION_SIZE; 907 phys += SUPERSECTION_SIZE; 908 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; 909 } while (addr != end); 910} 911#endif /* !CONFIG_ARM_LPAE */ 912 913static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md, 914 void *(*alloc)(unsigned long sz), 915 bool ng) 916{ 917 unsigned long addr, length, end; 918 phys_addr_t phys; 919 const struct mem_type *type; 920 pgd_t *pgd; 921 922 type = &mem_types[md->type]; 923 924#ifndef CONFIG_ARM_LPAE 925 /* 926 * Catch 36-bit addresses 927 */ 928 if (md->pfn >= 0x100000) { 929 create_36bit_mapping(mm, md, type, ng); 930 return; 931 } 932#endif 933 934 addr = md->virtual & PAGE_MASK; 935 phys = __pfn_to_phys(md->pfn); 936 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 937 938 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { 939 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n", 940 (long long)__pfn_to_phys(md->pfn), addr); 941 return; 942 } 943 944 pgd = pgd_offset(mm, addr); 945 end = addr + length; 946 do { 947 unsigned long next = pgd_addr_end(addr, end); 948 949 alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng); 950 951 phys += next - addr; 952 addr = next; 953 } while (pgd++, addr != end); 954} 955 956/* 957 * Create the page directory entries and any necessary 958 * page tables for the mapping specified by `md'. We 959 * are able to cope here with varying sizes and address 960 * offsets, and we take full advantage of sections and 961 * supersections. 962 */ 963static void __init create_mapping(struct map_desc *md) 964{ 965 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 966 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n", 967 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 968 return; 969 } 970 971 if (md->type == MT_DEVICE && 972 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START && 973 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { 974 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n", 975 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 976 } 977 978 __create_mapping(&init_mm, md, early_alloc, false); 979} 980 981void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md, 982 bool ng) 983{ 984#ifdef CONFIG_ARM_LPAE 985 p4d_t *p4d; 986 pud_t *pud; 987 988 p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual); 989 if (WARN_ON(!p4d)) 990 return; 991 pud = pud_alloc(mm, p4d, md->virtual); 992 if (WARN_ON(!pud)) 993 return; 994 pmd_alloc(mm, pud, 0); 995#endif 996 __create_mapping(mm, md, late_alloc, ng); 997} 998 999/* 1000 * Create the architecture specific mappings 1001 */ 1002void __init iotable_init(struct map_desc *io_desc, int nr) 1003{ 1004 struct map_desc *md; 1005 struct vm_struct *vm; 1006 struct static_vm *svm; 1007 1008 if (!nr) 1009 return; 1010 1011 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm)); 1012 if (!svm) 1013 panic("%s: Failed to allocate %zu bytes align=0x%zx\n", 1014 __func__, sizeof(*svm) * nr, __alignof__(*svm)); 1015 1016 for (md = io_desc; nr; md++, nr--) { 1017 create_mapping(md); 1018 1019 vm = &svm->vm; 1020 vm->addr = (void *)(md->virtual & PAGE_MASK); 1021 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 1022 vm->phys_addr = __pfn_to_phys(md->pfn); 1023 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 1024 vm->flags |= VM_ARM_MTYPE(md->type); 1025 vm->caller = iotable_init; 1026 add_static_vm_early(svm++); 1027 } 1028} 1029 1030void __init vm_reserve_area_early(unsigned long addr, unsigned long size, 1031 void *caller) 1032{ 1033 struct vm_struct *vm; 1034 struct static_vm *svm; 1035 1036 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm)); 1037 if (!svm) 1038 panic("%s: Failed to allocate %zu bytes align=0x%zx\n", 1039 __func__, sizeof(*svm), __alignof__(*svm)); 1040 1041 vm = &svm->vm; 1042 vm->addr = (void *)addr; 1043 vm->size = size; 1044 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; 1045 vm->caller = caller; 1046 add_static_vm_early(svm); 1047} 1048 1049#ifndef CONFIG_ARM_LPAE 1050 1051/* 1052 * The Linux PMD is made of two consecutive section entries covering 2MB 1053 * (see definition in include/asm/pgtable-2level.h). However a call to 1054 * create_mapping() may optimize static mappings by using individual 1055 * 1MB section mappings. This leaves the actual PMD potentially half 1056 * initialized if the top or bottom section entry isn't used, leaving it 1057 * open to problems if a subsequent ioremap() or vmalloc() tries to use 1058 * the virtual space left free by that unused section entry. 1059 * 1060 * Let's avoid the issue by inserting dummy vm entries covering the unused 1061 * PMD halves once the static mappings are in place. 1062 */ 1063 1064static void __init pmd_empty_section_gap(unsigned long addr) 1065{ 1066 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); 1067} 1068 1069static void __init fill_pmd_gaps(void) 1070{ 1071 struct static_vm *svm; 1072 struct vm_struct *vm; 1073 unsigned long addr, next = 0; 1074 pmd_t *pmd; 1075 1076 list_for_each_entry(svm, &static_vmlist, list) { 1077 vm = &svm->vm; 1078 addr = (unsigned long)vm->addr; 1079 if (addr < next) 1080 continue; 1081 1082 /* 1083 * Check if this vm starts on an odd section boundary. 1084 * If so and the first section entry for this PMD is free 1085 * then we block the corresponding virtual address. 1086 */ 1087 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 1088 pmd = pmd_off_k(addr); 1089 if (pmd_none(*pmd)) 1090 pmd_empty_section_gap(addr & PMD_MASK); 1091 } 1092 1093 /* 1094 * Then check if this vm ends on an odd section boundary. 1095 * If so and the second section entry for this PMD is empty 1096 * then we block the corresponding virtual address. 1097 */ 1098 addr += vm->size; 1099 if ((addr & ~PMD_MASK) == SECTION_SIZE) { 1100 pmd = pmd_off_k(addr) + 1; 1101 if (pmd_none(*pmd)) 1102 pmd_empty_section_gap(addr); 1103 } 1104 1105 /* no need to look at any vm entry until we hit the next PMD */ 1106 next = (addr + PMD_SIZE - 1) & PMD_MASK; 1107 } 1108} 1109 1110#else 1111#define fill_pmd_gaps() do { } while (0) 1112#endif 1113 1114#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) 1115static void __init pci_reserve_io(void) 1116{ 1117 struct static_vm *svm; 1118 1119 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); 1120 if (svm) 1121 return; 1122 1123 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); 1124} 1125#else 1126#define pci_reserve_io() do { } while (0) 1127#endif 1128 1129#ifdef CONFIG_DEBUG_LL 1130void __init debug_ll_io_init(void) 1131{ 1132 struct map_desc map; 1133 1134 debug_ll_addr(&map.pfn, &map.virtual); 1135 if (!map.pfn || !map.virtual) 1136 return; 1137 map.pfn = __phys_to_pfn(map.pfn); 1138 map.virtual &= PAGE_MASK; 1139 map.length = PAGE_SIZE; 1140 map.type = MT_DEVICE; 1141 iotable_init(&map, 1); 1142} 1143#endif 1144 1145static void * __initdata vmalloc_min = (void *)VMALLOC_DEFAULT_BASE; 1146 1147/* 1148 * vmalloc=size forces the vmalloc area to be exactly 'size' 1149 * bytes. This can be used to increase (or decrease) the vmalloc 1150 * area - the default is 240m. 1151 */ 1152static int __init early_vmalloc(char *arg) 1153{ 1154 unsigned long vmalloc_reserve = memparse(arg, NULL); 1155 1156 if (vmalloc_reserve < SZ_16M) { 1157 vmalloc_reserve = SZ_16M; 1158 pr_warn("vmalloc area too small, limiting to %luMB\n", 1159 vmalloc_reserve >> 20); 1160 } 1161 1162 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { 1163 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); 1164 pr_warn("vmalloc area is too big, limiting to %luMB\n", 1165 vmalloc_reserve >> 20); 1166 } 1167 1168 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); 1169 return 0; 1170} 1171early_param("vmalloc", early_vmalloc); 1172 1173phys_addr_t arm_lowmem_limit __initdata = 0; 1174 1175void __init adjust_lowmem_bounds(void) 1176{ 1177 phys_addr_t block_start, block_end, memblock_limit = 0; 1178 u64 vmalloc_limit, i; 1179 phys_addr_t lowmem_limit = 0; 1180 1181 /* 1182 * Let's use our own (unoptimized) equivalent of __pa() that is 1183 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4. 1184 * The result is used as the upper bound on physical memory address 1185 * and may itself be outside the valid range for which phys_addr_t 1186 * and therefore __pa() is defined. 1187 */ 1188 vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET; 1189 1190 /* 1191 * The first usable region must be PMD aligned. Mark its start 1192 * as MEMBLOCK_NOMAP if it isn't 1193 */ 1194 for_each_mem_range(i, &block_start, &block_end) { 1195 if (!IS_ALIGNED(block_start, PMD_SIZE)) { 1196 phys_addr_t len; 1197 1198 len = round_up(block_start, PMD_SIZE) - block_start; 1199 memblock_mark_nomap(block_start, len); 1200 } 1201 break; 1202 } 1203 1204 for_each_mem_range(i, &block_start, &block_end) { 1205 if (block_start < vmalloc_limit) { 1206 if (block_end > lowmem_limit) 1207 /* 1208 * Compare as u64 to ensure vmalloc_limit does 1209 * not get truncated. block_end should always 1210 * fit in phys_addr_t so there should be no 1211 * issue with assignment. 1212 */ 1213 lowmem_limit = min_t(u64, 1214 vmalloc_limit, 1215 block_end); 1216 1217 /* 1218 * Find the first non-pmd-aligned page, and point 1219 * memblock_limit at it. This relies on rounding the 1220 * limit down to be pmd-aligned, which happens at the 1221 * end of this function. 1222 * 1223 * With this algorithm, the start or end of almost any 1224 * bank can be non-pmd-aligned. The only exception is 1225 * that the start of the bank 0 must be section- 1226 * aligned, since otherwise memory would need to be 1227 * allocated when mapping the start of bank 0, which 1228 * occurs before any free memory is mapped. 1229 */ 1230 if (!memblock_limit) { 1231 if (!IS_ALIGNED(block_start, PMD_SIZE)) 1232 memblock_limit = block_start; 1233 else if (!IS_ALIGNED(block_end, PMD_SIZE)) 1234 memblock_limit = lowmem_limit; 1235 } 1236 1237 } 1238 } 1239 1240 arm_lowmem_limit = lowmem_limit; 1241 1242 high_memory = __va(arm_lowmem_limit - 1) + 1; 1243 1244 if (!memblock_limit) 1245 memblock_limit = arm_lowmem_limit; 1246 1247 /* 1248 * Round the memblock limit down to a pmd size. This 1249 * helps to ensure that we will allocate memory from the 1250 * last full pmd, which should be mapped. 1251 */ 1252 memblock_limit = round_down(memblock_limit, PMD_SIZE); 1253 1254 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) { 1255 if (memblock_end_of_DRAM() > arm_lowmem_limit) { 1256 phys_addr_t end = memblock_end_of_DRAM(); 1257 1258 pr_notice("Ignoring RAM at %pa-%pa\n", 1259 &memblock_limit, &end); 1260 pr_notice("Consider using a HIGHMEM enabled kernel.\n"); 1261 1262 memblock_remove(memblock_limit, end - memblock_limit); 1263 } 1264 } 1265 1266 memblock_set_current_limit(memblock_limit); 1267} 1268 1269static inline void prepare_page_table(void) 1270{ 1271 unsigned long addr; 1272 phys_addr_t end; 1273 1274 /* 1275 * Clear out all the mappings below the kernel image. 1276 */ 1277#ifdef CONFIG_KASAN 1278 /* 1279 * KASan's shadow memory inserts itself between the TASK_SIZE 1280 * and MODULES_VADDR. Do not clear the KASan shadow memory mappings. 1281 */ 1282 for (addr = 0; addr < KASAN_SHADOW_START; addr += PMD_SIZE) 1283 pmd_clear(pmd_off_k(addr)); 1284 /* 1285 * Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes 1286 * equal to MODULES_VADDR and then we exit the pmd clearing. If we 1287 * are using a thumb-compiled kernel, there there will be 8MB more 1288 * to clear as KASan always offset to 16 MB below MODULES_VADDR. 1289 */ 1290 for (addr = KASAN_SHADOW_END; addr < MODULES_VADDR; addr += PMD_SIZE) 1291 pmd_clear(pmd_off_k(addr)); 1292#else 1293 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) 1294 pmd_clear(pmd_off_k(addr)); 1295#endif 1296 1297#ifdef CONFIG_XIP_KERNEL 1298 /* The XIP kernel is mapped in the module area -- skip over it */ 1299 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK; 1300#endif 1301 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) 1302 pmd_clear(pmd_off_k(addr)); 1303 1304 /* 1305 * Find the end of the first block of lowmem. 1306 */ 1307 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; 1308 if (end >= arm_lowmem_limit) 1309 end = arm_lowmem_limit; 1310 1311 /* 1312 * Clear out all the kernel space mappings, except for the first 1313 * memory bank, up to the vmalloc region. 1314 */ 1315 for (addr = __phys_to_virt(end); 1316 addr < VMALLOC_START; addr += PMD_SIZE) 1317 pmd_clear(pmd_off_k(addr)); 1318} 1319 1320#ifdef CONFIG_ARM_LPAE 1321/* the first page is reserved for pgd */ 1322#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ 1323 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) 1324#else 1325#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) 1326#endif 1327 1328/* 1329 * Reserve the special regions of memory 1330 */ 1331void __init arm_mm_memblock_reserve(void) 1332{ 1333 /* 1334 * Reserve the page tables. These are already in use, 1335 * and can only be in node 0. 1336 */ 1337 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); 1338 1339#ifdef CONFIG_SA1111 1340 /* 1341 * Because of the SA1111 DMA bug, we want to preserve our 1342 * precious DMA-able memory... 1343 */ 1344 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); 1345#endif 1346} 1347 1348/* 1349 * Set up the device mappings. Since we clear out the page tables for all 1350 * mappings above VMALLOC_START, except early fixmap, we might remove debug 1351 * device mappings. This means earlycon can be used to debug this function 1352 * Any other function or debugging method which may touch any device _will_ 1353 * crash the kernel. 1354 */ 1355static void __init devicemaps_init(const struct machine_desc *mdesc) 1356{ 1357 struct map_desc map; 1358 unsigned long addr; 1359 void *vectors; 1360 1361 /* 1362 * Allocate the vector page early. 1363 */ 1364 vectors = early_alloc(PAGE_SIZE * 2); 1365 1366 early_trap_init(vectors); 1367 1368 /* 1369 * Clear page table except top pmd used by early fixmaps 1370 */ 1371 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE) 1372 pmd_clear(pmd_off_k(addr)); 1373 1374 if (__atags_pointer) { 1375 /* create a read-only mapping of the device tree */ 1376 map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK); 1377 map.virtual = FDT_FIXED_BASE; 1378 map.length = FDT_FIXED_SIZE; 1379 map.type = MT_MEMORY_RO; 1380 create_mapping(&map); 1381 } 1382 1383 /* 1384 * Map the kernel if it is XIP. 1385 * It is always first in the modulearea. 1386 */ 1387#ifdef CONFIG_XIP_KERNEL 1388 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 1389 map.virtual = MODULES_VADDR; 1390 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK; 1391 map.type = MT_ROM; 1392 create_mapping(&map); 1393#endif 1394 1395 /* 1396 * Map the cache flushing regions. 1397 */ 1398#ifdef FLUSH_BASE 1399 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 1400 map.virtual = FLUSH_BASE; 1401 map.length = SZ_1M; 1402 map.type = MT_CACHECLEAN; 1403 create_mapping(&map); 1404#endif 1405#ifdef FLUSH_BASE_MINICACHE 1406 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 1407 map.virtual = FLUSH_BASE_MINICACHE; 1408 map.length = SZ_1M; 1409 map.type = MT_MINICLEAN; 1410 create_mapping(&map); 1411#endif 1412 1413 /* 1414 * Create a mapping for the machine vectors at the high-vectors 1415 * location (0xffff0000). If we aren't using high-vectors, also 1416 * create a mapping at the low-vectors virtual address. 1417 */ 1418 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 1419 map.virtual = 0xffff0000; 1420 map.length = PAGE_SIZE; 1421#ifdef CONFIG_KUSER_HELPERS 1422 map.type = MT_HIGH_VECTORS; 1423#else 1424 map.type = MT_LOW_VECTORS; 1425#endif 1426 create_mapping(&map); 1427 1428 if (!vectors_high()) { 1429 map.virtual = 0; 1430 map.length = PAGE_SIZE * 2; 1431 map.type = MT_LOW_VECTORS; 1432 create_mapping(&map); 1433 } 1434 1435 /* Now create a kernel read-only mapping */ 1436 map.pfn += 1; 1437 map.virtual = 0xffff0000 + PAGE_SIZE; 1438 map.length = PAGE_SIZE; 1439 map.type = MT_LOW_VECTORS; 1440 create_mapping(&map); 1441 1442 /* 1443 * Ask the machine support to map in the statically mapped devices. 1444 */ 1445 if (mdesc->map_io) 1446 mdesc->map_io(); 1447 else 1448 debug_ll_io_init(); 1449 fill_pmd_gaps(); 1450 1451 /* Reserve fixed i/o space in VMALLOC region */ 1452 pci_reserve_io(); 1453 1454 /* 1455 * Finally flush the caches and tlb to ensure that we're in a 1456 * consistent state wrt the writebuffer. This also ensures that 1457 * any write-allocated cache lines in the vector page are written 1458 * back. After this point, we can start to touch devices again. 1459 */ 1460 local_flush_tlb_all(); 1461 flush_cache_all(); 1462 1463 /* Enable asynchronous aborts */ 1464 early_abt_enable(); 1465} 1466 1467static void __init kmap_init(void) 1468{ 1469#ifdef CONFIG_HIGHMEM 1470 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), 1471 PKMAP_BASE, _PAGE_KERNEL_TABLE); 1472#endif 1473 1474 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START, 1475 _PAGE_KERNEL_TABLE); 1476} 1477 1478static void __init map_lowmem(void) 1479{ 1480 phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE); 1481 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); 1482 phys_addr_t start, end; 1483 u64 i; 1484 1485 /* Map all the lowmem memory banks. */ 1486 for_each_mem_range(i, &start, &end) { 1487 struct map_desc map; 1488 1489 if (end > arm_lowmem_limit) 1490 end = arm_lowmem_limit; 1491 if (start >= end) 1492 break; 1493 1494 if (end < kernel_x_start) { 1495 map.pfn = __phys_to_pfn(start); 1496 map.virtual = __phys_to_virt(start); 1497 map.length = end - start; 1498 map.type = MT_MEMORY_RWX; 1499 1500 create_mapping(&map); 1501 } else if (start >= kernel_x_end) { 1502 map.pfn = __phys_to_pfn(start); 1503 map.virtual = __phys_to_virt(start); 1504 map.length = end - start; 1505 map.type = MT_MEMORY_RW; 1506 1507 create_mapping(&map); 1508 } else { 1509 /* This better cover the entire kernel */ 1510 if (start < kernel_x_start) { 1511 map.pfn = __phys_to_pfn(start); 1512 map.virtual = __phys_to_virt(start); 1513 map.length = kernel_x_start - start; 1514 map.type = MT_MEMORY_RW; 1515 1516 create_mapping(&map); 1517 } 1518 1519 map.pfn = __phys_to_pfn(kernel_x_start); 1520 map.virtual = __phys_to_virt(kernel_x_start); 1521 map.length = kernel_x_end - kernel_x_start; 1522 map.type = MT_MEMORY_RWX; 1523 1524 create_mapping(&map); 1525 1526 if (kernel_x_end < end) { 1527 map.pfn = __phys_to_pfn(kernel_x_end); 1528 map.virtual = __phys_to_virt(kernel_x_end); 1529 map.length = end - kernel_x_end; 1530 map.type = MT_MEMORY_RW; 1531 1532 create_mapping(&map); 1533 } 1534 } 1535 } 1536} 1537 1538#ifdef CONFIG_ARM_PV_FIXUP 1539typedef void pgtables_remap(long long offset, unsigned long pgd); 1540pgtables_remap lpae_pgtables_remap_asm; 1541 1542/* 1543 * early_paging_init() recreates boot time page table setup, allowing machines 1544 * to switch over to a high (>4G) address space on LPAE systems 1545 */ 1546static void __init early_paging_init(const struct machine_desc *mdesc) 1547{ 1548 pgtables_remap *lpae_pgtables_remap; 1549 unsigned long pa_pgd; 1550 unsigned int cr, ttbcr; 1551 long long offset; 1552 1553 if (!mdesc->pv_fixup) 1554 return; 1555 1556 offset = mdesc->pv_fixup(); 1557 if (offset == 0) 1558 return; 1559 1560 /* 1561 * Get the address of the remap function in the 1:1 identity 1562 * mapping setup by the early page table assembly code. We 1563 * must get this prior to the pv update. The following barrier 1564 * ensures that this is complete before we fixup any P:V offsets. 1565 */ 1566 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm); 1567 pa_pgd = __pa(swapper_pg_dir); 1568 barrier(); 1569 1570 pr_info("Switching physical address space to 0x%08llx\n", 1571 (u64)PHYS_OFFSET + offset); 1572 1573 /* Re-set the phys pfn offset, and the pv offset */ 1574 __pv_offset += offset; 1575 __pv_phys_pfn_offset += PFN_DOWN(offset); 1576 1577 /* Run the patch stub to update the constants */ 1578 fixup_pv_table(&__pv_table_begin, 1579 (&__pv_table_end - &__pv_table_begin) << 2); 1580 1581 /* 1582 * We changing not only the virtual to physical mapping, but also 1583 * the physical addresses used to access memory. We need to flush 1584 * all levels of cache in the system with caching disabled to 1585 * ensure that all data is written back, and nothing is prefetched 1586 * into the caches. We also need to prevent the TLB walkers 1587 * allocating into the caches too. Note that this is ARMv7 LPAE 1588 * specific. 1589 */ 1590 cr = get_cr(); 1591 set_cr(cr & ~(CR_I | CR_C)); 1592 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr)); 1593 asm volatile("mcr p15, 0, %0, c2, c0, 2" 1594 : : "r" (ttbcr & ~(3 << 8 | 3 << 10))); 1595 flush_cache_all(); 1596 1597 /* 1598 * Fixup the page tables - this must be in the idmap region as 1599 * we need to disable the MMU to do this safely, and hence it 1600 * needs to be assembly. It's fairly simple, as we're using the 1601 * temporary tables setup by the initial assembly code. 1602 */ 1603 lpae_pgtables_remap(offset, pa_pgd); 1604 1605 /* Re-enable the caches and cacheable TLB walks */ 1606 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr)); 1607 set_cr(cr); 1608} 1609 1610#else 1611 1612static void __init early_paging_init(const struct machine_desc *mdesc) 1613{ 1614 long long offset; 1615 1616 if (!mdesc->pv_fixup) 1617 return; 1618 1619 offset = mdesc->pv_fixup(); 1620 if (offset == 0) 1621 return; 1622 1623 pr_crit("Physical address space modification is only to support Keystone2.\n"); 1624 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n"); 1625 pr_crit("feature. Your kernel may crash now, have a good day.\n"); 1626 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1627} 1628 1629#endif 1630 1631static void __init early_fixmap_shutdown(void) 1632{ 1633 int i; 1634 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1); 1635 1636 pte_offset_fixmap = pte_offset_late_fixmap; 1637 pmd_clear(fixmap_pmd(va)); 1638 local_flush_tlb_kernel_page(va); 1639 1640 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) { 1641 pte_t *pte; 1642 struct map_desc map; 1643 1644 map.virtual = fix_to_virt(i); 1645 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual); 1646 1647 /* Only i/o device mappings are supported ATM */ 1648 if (pte_none(*pte) || 1649 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED) 1650 continue; 1651 1652 map.pfn = pte_pfn(*pte); 1653 map.type = MT_DEVICE; 1654 map.length = PAGE_SIZE; 1655 1656 create_mapping(&map); 1657 } 1658} 1659 1660/* 1661 * paging_init() sets up the page tables, initialises the zone memory 1662 * maps, and sets up the zero page, bad page and bad page tables. 1663 */ 1664void __init paging_init(const struct machine_desc *mdesc) 1665{ 1666 void *zero_page; 1667 1668 prepare_page_table(); 1669 map_lowmem(); 1670 memblock_set_current_limit(arm_lowmem_limit); 1671 dma_contiguous_remap(); 1672 early_fixmap_shutdown(); 1673 devicemaps_init(mdesc); 1674 kmap_init(); 1675 tcm_init(); 1676 1677 top_pmd = pmd_off_k(0xffff0000); 1678 1679 /* allocate the zero page. */ 1680 zero_page = early_alloc(PAGE_SIZE); 1681 1682 bootmem_init(); 1683 1684 empty_zero_page = virt_to_page(zero_page); 1685 __flush_dcache_page(NULL, empty_zero_page); 1686} 1687 1688void __init early_mm_init(const struct machine_desc *mdesc) 1689{ 1690 build_mem_type_table(); 1691 early_paging_init(mdesc); 1692} 1693 1694void set_pte_at(struct mm_struct *mm, unsigned long addr, 1695 pte_t *ptep, pte_t pteval) 1696{ 1697 unsigned long ext = 0; 1698 1699 if (addr < TASK_SIZE && pte_valid_user(pteval)) { 1700 if (!pte_special(pteval)) 1701 __sync_icache_dcache(pteval); 1702 ext |= PTE_EXT_NG; 1703 } 1704 1705 set_pte_ext(ptep, pteval, ext); 1706} 1707