18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * arch/arm/mach-tegra/reset.h 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * CPU reset dispatcher. 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Copyright (c) 2011, NVIDIA Corporation. 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#ifndef __MACH_TEGRA_RESET_H 118c2ecf20Sopenharmony_ci#define __MACH_TEGRA_RESET_H 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci#define TEGRA_RESET_MASK_PRESENT 0 148c2ecf20Sopenharmony_ci#define TEGRA_RESET_MASK_LP1 1 158c2ecf20Sopenharmony_ci#define TEGRA_RESET_MASK_LP2 2 168c2ecf20Sopenharmony_ci#define TEGRA_RESET_STARTUP_SECONDARY 3 178c2ecf20Sopenharmony_ci#define TEGRA_RESET_STARTUP_LP2 4 188c2ecf20Sopenharmony_ci#define TEGRA_RESET_STARTUP_LP1 5 198c2ecf20Sopenharmony_ci#define TEGRA_RESET_TF_PRESENT 6 208c2ecf20Sopenharmony_ci#define TEGRA_RESET_DATA_SIZE 7 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci#ifndef __ASSEMBLY__ 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci#include "irammap.h" 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ciextern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]; 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_civoid __tegra_cpu_reset_handler_start(void); 318c2ecf20Sopenharmony_civoid __tegra_cpu_reset_handler(void); 328c2ecf20Sopenharmony_civoid __tegra20_cpu1_resettable_status_offset(void); 338c2ecf20Sopenharmony_civoid __tegra_cpu_reset_handler_end(void); 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci#ifdef CONFIG_PM_SLEEP 368c2ecf20Sopenharmony_ci#define tegra_cpu_lp1_mask \ 378c2ecf20Sopenharmony_ci (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 388c2ecf20Sopenharmony_ci ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \ 398c2ecf20Sopenharmony_ci (u32)__tegra_cpu_reset_handler_start))) 408c2ecf20Sopenharmony_ci#define tegra_cpu_lp2_mask \ 418c2ecf20Sopenharmony_ci (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 428c2ecf20Sopenharmony_ci ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ 438c2ecf20Sopenharmony_ci (u32)__tegra_cpu_reset_handler_start))) 448c2ecf20Sopenharmony_ci#endif 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci#define tegra_cpu_reset_handler_offset \ 478c2ecf20Sopenharmony_ci ((u32)__tegra_cpu_reset_handler - \ 488c2ecf20Sopenharmony_ci (u32)__tegra_cpu_reset_handler_start) 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_ci#define tegra_cpu_reset_handler_size \ 518c2ecf20Sopenharmony_ci (__tegra_cpu_reset_handler_end - \ 528c2ecf20Sopenharmony_ci __tegra_cpu_reset_handler_start) 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_civoid __init tegra_cpu_reset_handler_init(void); 558c2ecf20Sopenharmony_ci 568c2ecf20Sopenharmony_ci#endif 578c2ecf20Sopenharmony_ci#endif 58