18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#ifndef __MACH_TEGRA_IRAMMAP_H 78c2ecf20Sopenharmony_ci#define __MACH_TEGRA_IRAMMAP_H 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#include <linux/sizes.h> 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* The first 1K of IRAM is permanently reserved for the CPU reset handler */ 128c2ecf20Sopenharmony_ci#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0 138c2ecf20Sopenharmony_ci#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci/* 168c2ecf20Sopenharmony_ci * This area is used for LPx resume vector, only while LPx power state is 178c2ecf20Sopenharmony_ci * active. At other times, the AVP may use this area for arbitrary purposes 188c2ecf20Sopenharmony_ci */ 198c2ecf20Sopenharmony_ci#define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K) 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci#endif 22