18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * arch/arm/mach-spear13XX/headsmp.S 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Picked from realview 68c2ecf20Sopenharmony_ci * Copyright (c) 2012 ST Microelectronics Limited 78c2ecf20Sopenharmony_ci * Shiraz Hashim <shiraz.linux.kernel@gmail.com> 88c2ecf20Sopenharmony_ci */ 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci#include <linux/linkage.h> 118c2ecf20Sopenharmony_ci#include <linux/init.h> 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci#include <asm/assembler.h> 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci __INIT 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci/* 188c2ecf20Sopenharmony_ci * spear13xx specific entry point for secondary CPUs. This provides 198c2ecf20Sopenharmony_ci * a "holding pen" into which all secondary cores are held until we're 208c2ecf20Sopenharmony_ci * ready for them to initialise. 218c2ecf20Sopenharmony_ci */ 228c2ecf20Sopenharmony_ciENTRY(spear13xx_secondary_startup) 238c2ecf20Sopenharmony_ci mrc p15, 0, r0, c0, c0, 5 248c2ecf20Sopenharmony_ci and r0, r0, #15 258c2ecf20Sopenharmony_ci adr_l r6, spear_pen_release 268c2ecf20Sopenharmony_cipen: ldr r7, [r6] 278c2ecf20Sopenharmony_ci cmp r7, r0 288c2ecf20Sopenharmony_ci bne pen 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci /* re-enable coherency */ 318c2ecf20Sopenharmony_ci mrc p15, 0, r0, c1, c0, 1 328c2ecf20Sopenharmony_ci orr r0, r0, #(1 << 6) | (1 << 0) 338c2ecf20Sopenharmony_ci mcr p15, 0, r0, c1, c0, 1 348c2ecf20Sopenharmony_ci /* 358c2ecf20Sopenharmony_ci * we've been released from the holding pen: secondary_stack 368c2ecf20Sopenharmony_ci * should now contain the SVC stack for this core 378c2ecf20Sopenharmony_ci */ 388c2ecf20Sopenharmony_ci b secondary_startup 398c2ecf20Sopenharmony_ciENDPROC(spear13xx_secondary_startup) 40