18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ 28c2ecf20Sopenharmony_ci * 38c2ecf20Sopenharmony_ci * Shared SCU setup for mach-shmobile 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2012 Bastian Hecht 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#include <linux/linkage.h> 98c2ecf20Sopenharmony_ci#include <linux/init.h> 108c2ecf20Sopenharmony_ci#include <asm/memory.h> 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci/* 138c2ecf20Sopenharmony_ci * Boot code for secondary CPUs. 148c2ecf20Sopenharmony_ci * 158c2ecf20Sopenharmony_ci * First we turn on L1 cache coherency for our CPU. Then we jump to 168c2ecf20Sopenharmony_ci * secondary_startup that invalidates the cache and hands over control 178c2ecf20Sopenharmony_ci * to the common ARM startup code. 188c2ecf20Sopenharmony_ci */ 198c2ecf20Sopenharmony_ciENTRY(shmobile_boot_scu) 208c2ecf20Sopenharmony_ci @ r0 = SCU base address 218c2ecf20Sopenharmony_ci mrc p15, 0, r1, c0, c0, 5 @ read MPIDR 228c2ecf20Sopenharmony_ci and r1, r1, #3 @ mask out cpu ID 238c2ecf20Sopenharmony_ci lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits 248c2ecf20Sopenharmony_ci ldr r2, [r0, #8] @ SCU Power Status Register 258c2ecf20Sopenharmony_ci mov r3, #3 268c2ecf20Sopenharmony_ci lsl r3, r3, r1 278c2ecf20Sopenharmony_ci bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) 288c2ecf20Sopenharmony_ci str r2, [r0, #8] @ write back 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_ci b secondary_startup 318c2ecf20Sopenharmony_ciENDPROC(shmobile_boot_scu) 32