1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (c) 2011 Samsung Electronics Co., Ltd.
4//		http://www.samsung.com
5//
6// Copyright 2008 Openmoko, Inc.
7// Copyright 2008 Simtec Electronics
8//	Ben Dooks <ben@simtec.co.uk>
9//	http://armlinux.simtec.co.uk/
10//
11// Common Codes for S3C64XX machines
12
13/*
14 * NOTE: Code in this file is not used when booting with Device Tree support.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/ioport.h>
22#include <linux/serial_core.h>
23#include <linux/serial_s3c.h>
24#include <linux/platform_device.h>
25#include <linux/reboot.h>
26#include <linux/io.h>
27#include <linux/clk/samsung.h>
28#include <linux/dma-mapping.h>
29#include <linux/irq.h>
30#include <linux/gpio.h>
31#include <linux/irqchip/arm-vic.h>
32#include <clocksource/samsung_pwm.h>
33
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/system_misc.h>
37
38#include "map.h"
39#include <mach/irqs.h>
40#include "regs-gpio.h"
41#include "gpio-samsung.h"
42
43#include "cpu.h"
44#include "devs.h"
45#include "pm.h"
46#include "gpio-cfg.h"
47#include "pwm-core.h"
48#include "regs-irqtype.h"
49#include "s3c64xx.h"
50#include "irq-uart-s3c64xx.h"
51
52/* External clock frequency */
53static unsigned long xtal_f __ro_after_init = 12000000;
54static unsigned long xusbxti_f __ro_after_init = 48000000;
55
56void __init s3c64xx_set_xtal_freq(unsigned long freq)
57{
58	xtal_f = freq;
59}
60
61void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
62{
63	xusbxti_f = freq;
64}
65
66/* uart registration process */
67
68static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
69{
70	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
71}
72
73/* table of supported CPUs */
74
75static const char name_s3c6400[] = "S3C6400";
76static const char name_s3c6410[] = "S3C6410";
77
78static struct cpu_table cpu_ids[] __initdata = {
79	{
80		.idcode		= S3C6400_CPU_ID,
81		.idmask		= S3C64XX_CPU_MASK,
82		.map_io		= s3c6400_map_io,
83		.init_uarts	= s3c64xx_init_uarts,
84		.init		= s3c6400_init,
85		.name		= name_s3c6400,
86	}, {
87		.idcode		= S3C6410_CPU_ID,
88		.idmask		= S3C64XX_CPU_MASK,
89		.map_io		= s3c6410_map_io,
90		.init_uarts	= s3c64xx_init_uarts,
91		.init		= s3c6410_init,
92		.name		= name_s3c6410,
93	},
94};
95
96/* minimal IO mapping */
97
98/*
99 * note, for the boot process to work we have to keep the UART
100 * virtual address aligned to an 1MiB boundary for the L1
101 * mapping the head code makes. We keep the UART virtual address
102 * aligned and add in the offset when we load the value here.
103 */
104#define UART_OFFS (S3C_PA_UART & 0xfffff)
105
106static struct map_desc s3c_iodesc[] __initdata = {
107	{
108		.virtual	= (unsigned long)S3C_VA_SYS,
109		.pfn		= __phys_to_pfn(S3C64XX_PA_SYSCON),
110		.length		= SZ_4K,
111		.type		= MT_DEVICE,
112	}, {
113		.virtual	= (unsigned long)S3C_VA_MEM,
114		.pfn		= __phys_to_pfn(S3C64XX_PA_SROM),
115		.length		= SZ_4K,
116		.type		= MT_DEVICE,
117	}, {
118		.virtual	= (unsigned long)(S3C_VA_UART + UART_OFFS),
119		.pfn		= __phys_to_pfn(S3C_PA_UART),
120		.length		= SZ_4K,
121		.type		= MT_DEVICE,
122	}, {
123		.virtual	= (unsigned long)VA_VIC0,
124		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC0),
125		.length		= SZ_16K,
126		.type		= MT_DEVICE,
127	}, {
128		.virtual	= (unsigned long)VA_VIC1,
129		.pfn		= __phys_to_pfn(S3C64XX_PA_VIC1),
130		.length		= SZ_16K,
131		.type		= MT_DEVICE,
132	}, {
133		.virtual	= (unsigned long)S3C_VA_TIMER,
134		.pfn		= __phys_to_pfn(S3C_PA_TIMER),
135		.length		= SZ_16K,
136		.type		= MT_DEVICE,
137	}, {
138		.virtual	= (unsigned long)S3C64XX_VA_GPIO,
139		.pfn		= __phys_to_pfn(S3C64XX_PA_GPIO),
140		.length		= SZ_4K,
141		.type		= MT_DEVICE,
142	}, {
143		.virtual	= (unsigned long)S3C64XX_VA_MODEM,
144		.pfn		= __phys_to_pfn(S3C64XX_PA_MODEM),
145		.length		= SZ_4K,
146		.type		= MT_DEVICE,
147	}, {
148		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
149		.pfn		= __phys_to_pfn(S3C64XX_PA_WATCHDOG),
150		.length		= SZ_4K,
151		.type		= MT_DEVICE,
152	}, {
153		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
154		.pfn		= __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
155		.length		= SZ_1K,
156		.type		= MT_DEVICE,
157	},
158};
159
160static struct bus_type s3c64xx_subsys = {
161	.name		= "s3c64xx-core",
162	.dev_name	= "s3c64xx-core",
163};
164
165static struct device s3c64xx_dev = {
166	.bus	= &s3c64xx_subsys,
167};
168
169static struct samsung_pwm_variant s3c64xx_pwm_variant = {
170	.bits		= 32,
171	.div_base	= 0,
172	.has_tint_cstat	= true,
173	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
174};
175
176void __init s3c64xx_set_timer_source(enum s3c64xx_timer_mode event,
177				     enum s3c64xx_timer_mode source)
178{
179	s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
180	s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
181}
182
183void __init s3c64xx_timer_init(void)
184{
185	unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
186		IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
187		IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
188	};
189
190	samsung_pwm_clocksource_init(S3C_VA_TIMER,
191					timer_irqs, &s3c64xx_pwm_variant);
192}
193
194/* read cpu identification code */
195
196void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
197{
198	/* initialise the io descriptors we need for initialisation */
199	iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
200	iotable_init(mach_desc, size);
201
202	/* detect cpu id */
203	s3c64xx_init_cpu();
204
205	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
206
207	samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
208}
209
210static __init int s3c64xx_dev_init(void)
211{
212	/* Not applicable when using DT. */
213	if (of_have_populated_dt() || !soc_is_s3c64xx())
214		return 0;
215
216	subsys_system_register(&s3c64xx_subsys, NULL);
217	return device_register(&s3c64xx_dev);
218}
219core_initcall(s3c64xx_dev_init);
220
221/*
222 * setup the sources the vic should advertise resume
223 * for, even though it is not doing the wake
224 * (set_irq_wake needs to be valid)
225 */
226#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
227#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) |	\
228			 1 << (IRQ_PENDN - IRQ_VIC1_BASE) |	\
229			 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |	\
230			 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |	\
231			 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
232
233void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
234{
235	s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
236
237	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
238
239	/* initialise the pair of VICs */
240	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
241	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
242}
243
244#define eint_offset(irq)	((irq) - IRQ_EINT(0))
245#define eint_irq_to_bit(irq)	((u32)(1 << eint_offset(irq)))
246
247static inline void s3c_irq_eint_mask(struct irq_data *data)
248{
249	u32 mask;
250
251	mask = __raw_readl(S3C64XX_EINT0MASK);
252	mask |= (u32)data->chip_data;
253	__raw_writel(mask, S3C64XX_EINT0MASK);
254}
255
256static void s3c_irq_eint_unmask(struct irq_data *data)
257{
258	u32 mask;
259
260	mask = __raw_readl(S3C64XX_EINT0MASK);
261	mask &= ~((u32)data->chip_data);
262	__raw_writel(mask, S3C64XX_EINT0MASK);
263}
264
265static inline void s3c_irq_eint_ack(struct irq_data *data)
266{
267	__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
268}
269
270static void s3c_irq_eint_maskack(struct irq_data *data)
271{
272	/* compiler should in-line these */
273	s3c_irq_eint_mask(data);
274	s3c_irq_eint_ack(data);
275}
276
277static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
278{
279	int offs = eint_offset(data->irq);
280	int pin, pin_val;
281	int shift;
282	u32 ctrl, mask;
283	u32 newvalue = 0;
284	void __iomem *reg;
285
286	if (offs > 27)
287		return -EINVAL;
288
289	if (offs <= 15)
290		reg = S3C64XX_EINT0CON0;
291	else
292		reg = S3C64XX_EINT0CON1;
293
294	switch (type) {
295	case IRQ_TYPE_NONE:
296		printk(KERN_WARNING "No edge setting!\n");
297		break;
298
299	case IRQ_TYPE_EDGE_RISING:
300		newvalue = S3C2410_EXTINT_RISEEDGE;
301		break;
302
303	case IRQ_TYPE_EDGE_FALLING:
304		newvalue = S3C2410_EXTINT_FALLEDGE;
305		break;
306
307	case IRQ_TYPE_EDGE_BOTH:
308		newvalue = S3C2410_EXTINT_BOTHEDGE;
309		break;
310
311	case IRQ_TYPE_LEVEL_LOW:
312		newvalue = S3C2410_EXTINT_LOWLEV;
313		break;
314
315	case IRQ_TYPE_LEVEL_HIGH:
316		newvalue = S3C2410_EXTINT_HILEV;
317		break;
318
319	default:
320		printk(KERN_ERR "No such irq type %d", type);
321		return -1;
322	}
323
324	if (offs <= 15)
325		shift = (offs / 2) * 4;
326	else
327		shift = ((offs - 16) / 2) * 4;
328	mask = 0x7 << shift;
329
330	ctrl = __raw_readl(reg);
331	ctrl &= ~mask;
332	ctrl |= newvalue << shift;
333	__raw_writel(ctrl, reg);
334
335	/* set the GPIO pin appropriately */
336
337	if (offs < 16) {
338		pin = S3C64XX_GPN(offs);
339		pin_val = S3C_GPIO_SFN(2);
340	} else if (offs < 23) {
341		pin = S3C64XX_GPL(offs + 8 - 16);
342		pin_val = S3C_GPIO_SFN(3);
343	} else {
344		pin = S3C64XX_GPM(offs - 23);
345		pin_val = S3C_GPIO_SFN(3);
346	}
347
348	s3c_gpio_cfgpin(pin, pin_val);
349
350	return 0;
351}
352
353static struct irq_chip s3c_irq_eint = {
354	.name		= "s3c-eint",
355	.irq_mask	= s3c_irq_eint_mask,
356	.irq_unmask	= s3c_irq_eint_unmask,
357	.irq_mask_ack	= s3c_irq_eint_maskack,
358	.irq_ack	= s3c_irq_eint_ack,
359	.irq_set_type	= s3c_irq_eint_set_type,
360	.irq_set_wake	= s3c_irqext_wake,
361};
362
363/* s3c_irq_demux_eint
364 *
365 * This function demuxes the IRQ from the group0 external interrupts,
366 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
367 * the specific handlers s3c_irq_demux_eintX_Y.
368 */
369static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
370{
371	u32 status = __raw_readl(S3C64XX_EINT0PEND);
372	u32 mask = __raw_readl(S3C64XX_EINT0MASK);
373	unsigned int irq;
374
375	status &= ~mask;
376	status >>= start;
377	status &= (1 << (end - start + 1)) - 1;
378
379	for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
380		if (status & 1)
381			generic_handle_irq(irq);
382
383		status >>= 1;
384	}
385}
386
387static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
388{
389	s3c_irq_demux_eint(0, 3);
390}
391
392static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
393{
394	s3c_irq_demux_eint(4, 11);
395}
396
397static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
398{
399	s3c_irq_demux_eint(12, 19);
400}
401
402static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
403{
404	s3c_irq_demux_eint(20, 27);
405}
406
407static int __init s3c64xx_init_irq_eint(void)
408{
409	int irq;
410
411	/* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
412	if (of_have_populated_dt() || !soc_is_s3c64xx())
413		return -ENODEV;
414
415	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
416		irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
417		irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
418		irq_clear_status_flags(irq, IRQ_NOREQUEST);
419	}
420
421	irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
422	irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
423	irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
424	irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
425
426	return 0;
427}
428arch_initcall(s3c64xx_init_irq_eint);
429