1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
4 *	http://armlinux.simtec.co.uk/
5 *
6 * S3C2410 clock register definitions
7 */
8
9#ifndef __ASM_ARM_REGS_CLOCK
10#define __ASM_ARM_REGS_CLOCK
11
12#include "map.h"
13
14#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
15
16#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
17
18#define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
19#define S3C2410_MPLLCON	    S3C2410_CLKREG(0x04)
20#define S3C2410_UPLLCON	    S3C2410_CLKREG(0x08)
21#define S3C2410_CLKCON	    S3C2410_CLKREG(0x0C)
22#define S3C2410_CLKSLOW	    S3C2410_CLKREG(0x10)
23#define S3C2410_CLKDIVN	    S3C2410_CLKREG(0x14)
24
25#define S3C2410_CLKCON_IDLE	     (1<<2)
26#define S3C2410_CLKCON_POWER	     (1<<3)
27#define S3C2410_CLKCON_NAND	     (1<<4)
28#define S3C2410_CLKCON_LCDC	     (1<<5)
29#define S3C2410_CLKCON_USBH	     (1<<6)
30#define S3C2410_CLKCON_USBD	     (1<<7)
31#define S3C2410_CLKCON_PWMT	     (1<<8)
32#define S3C2410_CLKCON_SDI	     (1<<9)
33#define S3C2410_CLKCON_UART0	     (1<<10)
34#define S3C2410_CLKCON_UART1	     (1<<11)
35#define S3C2410_CLKCON_UART2	     (1<<12)
36#define S3C2410_CLKCON_GPIO	     (1<<13)
37#define S3C2410_CLKCON_RTC	     (1<<14)
38#define S3C2410_CLKCON_ADC	     (1<<15)
39#define S3C2410_CLKCON_IIC	     (1<<16)
40#define S3C2410_CLKCON_IIS	     (1<<17)
41#define S3C2410_CLKCON_SPI	     (1<<18)
42
43#define S3C2410_CLKDIVN_PDIVN	     (1<<0)
44#define S3C2410_CLKDIVN_HDIVN	     (1<<1)
45
46#define S3C2410_CLKSLOW_UCLK_OFF	(1<<7)
47#define S3C2410_CLKSLOW_MPLL_OFF	(1<<5)
48#define S3C2410_CLKSLOW_SLOW		(1<<4)
49#define S3C2410_CLKSLOW_SLOWVAL(x)	(x)
50#define S3C2410_CLKSLOW_GET_SLOWVAL(x)	((x) & 7)
51
52#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
53
54/* extra registers */
55#define S3C2440_CAMDIVN	    S3C2410_CLKREG(0x18)
56
57#define S3C2440_CLKCON_CAMERA        (1<<19)
58#define S3C2440_CLKCON_AC97          (1<<20)
59
60#define S3C2440_CLKDIVN_PDIVN	     (1<<0)
61#define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
62#define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
63#define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
64#define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
65#define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
66#define S3C2440_CLKDIVN_UCLK         (1<<3)
67
68#define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
69#define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
70#define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
71#define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
72#define S3C2440_CAMDIVN_DVSEN        (1<<12)
73
74#define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)
75
76#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
77
78#if defined(CONFIG_CPU_S3C2412)
79
80#define S3C2412_OSCSET		S3C2410_CLKREG(0x18)
81#define S3C2412_CLKSRC		S3C2410_CLKREG(0x1C)
82
83#define S3C2412_PLLCON_OFF		(1<<20)
84
85#define S3C2412_CLKDIVN_PDIVN		(1<<2)
86#define S3C2412_CLKDIVN_HDIVN_MASK	(3<<0)
87#define S3C2412_CLKDIVN_ARMDIVN		(1<<3)
88#define S3C2412_CLKDIVN_DVSEN		(1<<4)
89#define S3C2412_CLKDIVN_HALFHCLK	(1<<5)
90#define S3C2412_CLKDIVN_USB48DIV	(1<<6)
91#define S3C2412_CLKDIVN_UARTDIV_MASK	(15<<8)
92#define S3C2412_CLKDIVN_UARTDIV_SHIFT	(8)
93#define S3C2412_CLKDIVN_I2SDIV_MASK	(15<<12)
94#define S3C2412_CLKDIVN_I2SDIV_SHIFT	(12)
95#define S3C2412_CLKDIVN_CAMDIV_MASK	(15<<16)
96#define S3C2412_CLKDIVN_CAMDIV_SHIFT	(16)
97
98#define S3C2412_CLKCON_WDT		(1<<28)
99#define S3C2412_CLKCON_SPI		(1<<27)
100#define S3C2412_CLKCON_IIS		(1<<26)
101#define S3C2412_CLKCON_IIC		(1<<25)
102#define S3C2412_CLKCON_ADC		(1<<24)
103#define S3C2412_CLKCON_RTC		(1<<23)
104#define S3C2412_CLKCON_GPIO		(1<<22)
105#define S3C2412_CLKCON_UART2		(1<<21)
106#define S3C2412_CLKCON_UART1		(1<<20)
107#define S3C2412_CLKCON_UART0		(1<<19)
108#define S3C2412_CLKCON_SDI		(1<<18)
109#define S3C2412_CLKCON_PWMT		(1<<17)
110#define S3C2412_CLKCON_USBD		(1<<16)
111#define S3C2412_CLKCON_CAMCLK		(1<<15)
112#define S3C2412_CLKCON_UARTCLK		(1<<14)
113/* missing 13 */
114#define S3C2412_CLKCON_USB_HOST48	(1<<12)
115#define S3C2412_CLKCON_USB_DEV48	(1<<11)
116#define S3C2412_CLKCON_HCLKdiv2		(1<<10)
117#define S3C2412_CLKCON_HCLKx2		(1<<9)
118#define S3C2412_CLKCON_SDRAM		(1<<8)
119/* missing 7 */
120#define S3C2412_CLKCON_USBH		S3C2410_CLKCON_USBH
121#define S3C2412_CLKCON_LCDC		S3C2410_CLKCON_LCDC
122#define S3C2412_CLKCON_NAND		S3C2410_CLKCON_NAND
123#define S3C2412_CLKCON_DMA3		(1<<3)
124#define S3C2412_CLKCON_DMA2		(1<<2)
125#define S3C2412_CLKCON_DMA1		(1<<1)
126#define S3C2412_CLKCON_DMA0		(1<<0)
127
128/* clock sourec controls */
129
130#define S3C2412_CLKSRC_EXTCLKDIV_MASK		(7 << 0)
131#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT		(0)
132#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV	(1<<3)
133#define S3C2412_CLKSRC_MSYSCLK_MPLL		(1<<4)
134#define S3C2412_CLKSRC_USYSCLK_UPLL		(1<<5)
135#define S3C2412_CLKSRC_UARTCLK_MPLL		(1<<8)
136#define S3C2412_CLKSRC_I2SCLK_MPLL		(1<<9)
137#define S3C2412_CLKSRC_USBCLK_HCLK		(1<<10)
138#define S3C2412_CLKSRC_CAMCLK_HCLK		(1<<11)
139#define S3C2412_CLKSRC_UREFCLK_EXTCLK	(1<<12)
140#define S3C2412_CLKSRC_EREFCLK_EXTCLK	(1<<14)
141
142#endif /* CONFIG_CPU_S3C2412 */
143
144#define S3C2416_CLKDIV2		S3C2410_CLKREG(0x28)
145
146#endif /* __ASM_ARM_REGS_CLOCK */
147