1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Device Tree support for Rockchip SoCs
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/of_clk.h>
13#include <linux/of_platform.h>
14#include <linux/irqchip.h>
15#include <linux/clocksource.h>
16#include <linux/mfd/syscon.h>
17#include <linux/regmap.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/hardware/cache-l2x0.h>
21#include "core.h"
22#include "pm.h"
23
24#define RK3288_TIMER6_7_PHYS 0xff810000
25
26static void __init rockchip_timer_init(void)
27{
28	if (of_machine_is_compatible("rockchip,rk3288")) {
29		void __iomem *reg_base;
30
31		/*
32		 * Most/all uboot versions for rk3288 don't enable timer7
33		 * which is needed for the architected timer to work.
34		 * So make sure it is running during early boot.
35		 */
36		reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
37		if (reg_base) {
38			writel(0, reg_base + 0x30);
39			writel(0xffffffff, reg_base + 0x20);
40			writel(0xffffffff, reg_base + 0x24);
41			writel(1, reg_base + 0x30);
42			dsb();
43			iounmap(reg_base);
44		} else {
45			pr_err("rockchip: could not map timer7 registers\n");
46		}
47	}
48
49	of_clk_init(NULL);
50	timer_probe();
51}
52
53static void __init rockchip_dt_init(void)
54{
55	rockchip_suspend_init();
56}
57
58static const char * const rockchip_board_dt_compat[] = {
59	"rockchip,rk2928",
60	"rockchip,rk3066a",
61	"rockchip,rk3066b",
62	"rockchip,rk3188",
63	"rockchip,rk3228",
64	"rockchip,rk3288",
65	"rockchip,rv1108",
66	NULL,
67};
68
69DT_MACHINE_START(ROCKCHIP_DT, "Rockchip (Device Tree)")
70	.l2c_aux_val	= 0,
71	.l2c_aux_mask	= ~0,
72	.init_time	= rockchip_timer_init,
73	.dt_compat	= rockchip_board_dt_compat,
74	.init_machine	= rockchip_dt_init,
75MACHINE_END
76