1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-pxa/lpd270.c
4 *
5 * Support for the LogicPD PXA270 Card Engine.
6 * Derived from the mainstone code, which carries these notices:
7 *
8 * Author:	Nicolas Pitre
9 * Created:	Nov 05, 2002
10 * Copyright:	MontaVista Software Inc.
11 */
12#include <linux/gpio.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/syscore_ops.h>
16#include <linux/interrupt.h>
17#include <linux/sched.h>
18#include <linux/bitops.h>
19#include <linux/fb.h>
20#include <linux/ioport.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/partitions.h>
23#include <linux/pwm.h>
24#include <linux/pwm_backlight.h>
25#include <linux/smc91x.h>
26
27#include <asm/types.h>
28#include <asm/setup.h>
29#include <asm/memory.h>
30#include <asm/mach-types.h>
31#include <mach/hardware.h>
32#include <asm/irq.h>
33#include <linux/sizes.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38#include <asm/mach/flash.h>
39
40#include "pxa27x.h"
41#include "lpd270.h"
42#include <mach/audio.h>
43#include <linux/platform_data/video-pxafb.h>
44#include <linux/platform_data/mmc-pxamci.h>
45#include <linux/platform_data/irda-pxaficp.h>
46#include <linux/platform_data/usb-ohci-pxa27x.h>
47#include <mach/smemc.h>
48
49#include "generic.h"
50#include "devices.h"
51
52static unsigned long lpd270_pin_config[] __initdata = {
53	/* Chip Selects */
54	GPIO15_nCS_1,	/* Mainboard Flash */
55	GPIO78_nCS_2,	/* CPLD + Ethernet */
56
57	/* LCD - 16bpp Active TFT */
58	GPIO58_LCD_LDD_0,
59	GPIO59_LCD_LDD_1,
60	GPIO60_LCD_LDD_2,
61	GPIO61_LCD_LDD_3,
62	GPIO62_LCD_LDD_4,
63	GPIO63_LCD_LDD_5,
64	GPIO64_LCD_LDD_6,
65	GPIO65_LCD_LDD_7,
66	GPIO66_LCD_LDD_8,
67	GPIO67_LCD_LDD_9,
68	GPIO68_LCD_LDD_10,
69	GPIO69_LCD_LDD_11,
70	GPIO70_LCD_LDD_12,
71	GPIO71_LCD_LDD_13,
72	GPIO72_LCD_LDD_14,
73	GPIO73_LCD_LDD_15,
74	GPIO74_LCD_FCLK,
75	GPIO75_LCD_LCLK,
76	GPIO76_LCD_PCLK,
77	GPIO77_LCD_BIAS,
78	GPIO16_PWM0_OUT,	/* Backlight */
79
80	/* USB Host */
81	GPIO88_USBH1_PWR,
82	GPIO89_USBH1_PEN,
83
84	/* AC97 */
85	GPIO28_AC97_BITCLK,
86	GPIO29_AC97_SDATA_IN_0,
87	GPIO30_AC97_SDATA_OUT,
88	GPIO31_AC97_SYNC,
89	GPIO45_AC97_SYSCLK,
90
91	GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
92};
93
94static unsigned int lpd270_irq_enabled;
95
96static void lpd270_mask_irq(struct irq_data *d)
97{
98	int lpd270_irq = d->irq - LPD270_IRQ(0);
99
100	__raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
101
102	lpd270_irq_enabled &= ~(1 << lpd270_irq);
103	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
104}
105
106static void lpd270_unmask_irq(struct irq_data *d)
107{
108	int lpd270_irq = d->irq - LPD270_IRQ(0);
109
110	lpd270_irq_enabled |= 1 << lpd270_irq;
111	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
112}
113
114static struct irq_chip lpd270_irq_chip = {
115	.name		= "CPLD",
116	.irq_ack	= lpd270_mask_irq,
117	.irq_mask	= lpd270_mask_irq,
118	.irq_unmask	= lpd270_unmask_irq,
119};
120
121static void lpd270_irq_handler(struct irq_desc *desc)
122{
123	unsigned int irq;
124	unsigned long pending;
125
126	pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
127	do {
128		/* clear useless edge notification */
129		desc->irq_data.chip->irq_ack(&desc->irq_data);
130		if (likely(pending)) {
131			irq = LPD270_IRQ(0) + __ffs(pending);
132			generic_handle_irq(irq);
133
134			pending = __raw_readw(LPD270_INT_STATUS) &
135						lpd270_irq_enabled;
136		}
137	} while (pending);
138}
139
140static void __init lpd270_init_irq(void)
141{
142	int irq;
143
144	pxa27x_init_irq();
145
146	__raw_writew(0, LPD270_INT_MASK);
147	__raw_writew(0, LPD270_INT_STATUS);
148
149	/* setup extra LogicPD PXA270 irqs */
150	for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
151		irq_set_chip_and_handler(irq, &lpd270_irq_chip,
152					 handle_level_irq);
153		irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
154	}
155	irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
156	irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
157}
158
159
160#ifdef CONFIG_PM
161static void lpd270_irq_resume(void)
162{
163	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
164}
165
166static struct syscore_ops lpd270_irq_syscore_ops = {
167	.resume = lpd270_irq_resume,
168};
169
170static int __init lpd270_irq_device_init(void)
171{
172	if (machine_is_logicpd_pxa270()) {
173		register_syscore_ops(&lpd270_irq_syscore_ops);
174		return 0;
175	}
176	return -ENODEV;
177}
178
179device_initcall(lpd270_irq_device_init);
180#endif
181
182
183static struct resource smc91x_resources[] = {
184	[0] = {
185		.start	= LPD270_ETH_PHYS,
186		.end	= (LPD270_ETH_PHYS + 0xfffff),
187		.flags	= IORESOURCE_MEM,
188	},
189	[1] = {
190		.start	= LPD270_ETHERNET_IRQ,
191		.end	= LPD270_ETHERNET_IRQ,
192		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
193	},
194};
195
196struct smc91x_platdata smc91x_platdata = {
197	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
198};
199
200static struct platform_device smc91x_device = {
201	.name		= "smc91x",
202	.id		= 0,
203	.num_resources	= ARRAY_SIZE(smc91x_resources),
204	.resource	= smc91x_resources,
205	.dev.platform_data = &smc91x_platdata,
206};
207
208static struct resource lpd270_flash_resources[] = {
209	[0] = {
210		.start	= PXA_CS0_PHYS,
211		.end	= PXA_CS0_PHYS + SZ_64M - 1,
212		.flags	= IORESOURCE_MEM,
213	},
214	[1] = {
215		.start	= PXA_CS1_PHYS,
216		.end	= PXA_CS1_PHYS + SZ_64M - 1,
217		.flags	= IORESOURCE_MEM,
218	},
219};
220
221static struct mtd_partition lpd270_flash0_partitions[] = {
222	{
223		.name =		"Bootloader",
224		.size =		0x00040000,
225		.offset =	0,
226		.mask_flags =	MTD_WRITEABLE  /* force read-only */
227	}, {
228		.name =		"Kernel",
229		.size =		0x00400000,
230		.offset =	0x00040000,
231	}, {
232		.name =		"Filesystem",
233		.size =		MTDPART_SIZ_FULL,
234		.offset =	0x00440000
235	},
236};
237
238static struct flash_platform_data lpd270_flash_data[2] = {
239	{
240		.name		= "processor-flash",
241		.map_name	= "cfi_probe",
242		.parts		= lpd270_flash0_partitions,
243		.nr_parts	= ARRAY_SIZE(lpd270_flash0_partitions),
244	}, {
245		.name		= "mainboard-flash",
246		.map_name	= "cfi_probe",
247		.parts		= NULL,
248		.nr_parts	= 0,
249	}
250};
251
252static struct platform_device lpd270_flash_device[2] = {
253	{
254		.name		= "pxa2xx-flash",
255		.id		= 0,
256		.dev = {
257			.platform_data	= &lpd270_flash_data[0],
258		},
259		.resource	= &lpd270_flash_resources[0],
260		.num_resources	= 1,
261	}, {
262		.name		= "pxa2xx-flash",
263		.id		= 1,
264		.dev = {
265			.platform_data	= &lpd270_flash_data[1],
266		},
267		.resource	= &lpd270_flash_resources[1],
268		.num_resources	= 1,
269	},
270};
271
272static struct pwm_lookup lpd270_pwm_lookup[] = {
273	PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
274		   PWM_POLARITY_NORMAL),
275};
276
277static struct platform_pwm_backlight_data lpd270_backlight_data = {
278	.max_brightness	= 1,
279	.dft_brightness	= 1,
280};
281
282static struct platform_device lpd270_backlight_device = {
283	.name		= "pwm-backlight",
284	.dev		= {
285		.parent	= &pxa27x_device_pwm0.dev,
286		.platform_data = &lpd270_backlight_data,
287	},
288};
289
290/* 5.7" TFT QVGA (LoLo display number 1) */
291static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
292	.pixclock		= 150000,
293	.xres			= 320,
294	.yres			= 240,
295	.bpp			= 16,
296	.hsync_len		= 0x14,
297	.left_margin		= 0x28,
298	.right_margin		= 0x0a,
299	.vsync_len		= 0x02,
300	.upper_margin		= 0x08,
301	.lower_margin		= 0x14,
302	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
303};
304
305static struct pxafb_mach_info sharp_lq057q3dc02 = {
306	.modes			= &sharp_lq057q3dc02_mode,
307	.num_modes		= 1,
308	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
309				  LCD_ALTERNATE_MAPPING,
310};
311
312/* 12.1" TFT SVGA (LoLo display number 2) */
313static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
314	.pixclock		= 50000,
315	.xres			= 800,
316	.yres			= 600,
317	.bpp			= 16,
318	.hsync_len		= 0x05,
319	.left_margin		= 0x52,
320	.right_margin		= 0x05,
321	.vsync_len		= 0x04,
322	.upper_margin		= 0x14,
323	.lower_margin		= 0x0a,
324	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
325};
326
327static struct pxafb_mach_info sharp_lq121s1dg31 = {
328	.modes			= &sharp_lq121s1dg31_mode,
329	.num_modes		= 1,
330	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
331				  LCD_ALTERNATE_MAPPING,
332};
333
334/* 3.6" TFT QVGA (LoLo display number 3) */
335static struct pxafb_mode_info sharp_lq036q1da01_mode = {
336	.pixclock		= 150000,
337	.xres			= 320,
338	.yres			= 240,
339	.bpp			= 16,
340	.hsync_len		= 0x0e,
341	.left_margin		= 0x04,
342	.right_margin		= 0x0a,
343	.vsync_len		= 0x03,
344	.upper_margin		= 0x03,
345	.lower_margin		= 0x03,
346	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
347};
348
349static struct pxafb_mach_info sharp_lq036q1da01 = {
350	.modes			= &sharp_lq036q1da01_mode,
351	.num_modes		= 1,
352	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
353				  LCD_ALTERNATE_MAPPING,
354};
355
356/* 6.4" TFT VGA (LoLo display number 5) */
357static struct pxafb_mode_info sharp_lq64d343_mode = {
358	.pixclock		= 25000,
359	.xres			= 640,
360	.yres			= 480,
361	.bpp			= 16,
362	.hsync_len		= 0x31,
363	.left_margin		= 0x89,
364	.right_margin		= 0x19,
365	.vsync_len		= 0x12,
366	.upper_margin		= 0x22,
367	.lower_margin		= 0x00,
368	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
369};
370
371static struct pxafb_mach_info sharp_lq64d343 = {
372	.modes			= &sharp_lq64d343_mode,
373	.num_modes		= 1,
374	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
375				  LCD_ALTERNATE_MAPPING,
376};
377
378/* 10.4" TFT VGA (LoLo display number 7) */
379static struct pxafb_mode_info sharp_lq10d368_mode = {
380	.pixclock		= 25000,
381	.xres			= 640,
382	.yres			= 480,
383	.bpp			= 16,
384	.hsync_len		= 0x31,
385	.left_margin		= 0x89,
386	.right_margin		= 0x19,
387	.vsync_len		= 0x12,
388	.upper_margin		= 0x22,
389	.lower_margin		= 0x00,
390	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
391};
392
393static struct pxafb_mach_info sharp_lq10d368 = {
394	.modes			= &sharp_lq10d368_mode,
395	.num_modes		= 1,
396	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
397				  LCD_ALTERNATE_MAPPING,
398};
399
400/* 3.5" TFT QVGA (LoLo display number 8) */
401static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
402	.pixclock		= 150000,
403	.xres			= 240,
404	.yres			= 320,
405	.bpp			= 16,
406	.hsync_len		= 0x0e,
407	.left_margin		= 0x0a,
408	.right_margin		= 0x0a,
409	.vsync_len		= 0x03,
410	.upper_margin		= 0x05,
411	.lower_margin		= 0x14,
412	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
413};
414
415static struct pxafb_mach_info sharp_lq035q7db02_20 = {
416	.modes			= &sharp_lq035q7db02_20_mode,
417	.num_modes		= 1,
418	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
419				  LCD_ALTERNATE_MAPPING,
420};
421
422static struct pxafb_mach_info *lpd270_lcd_to_use;
423
424static int __init lpd270_set_lcd(char *str)
425{
426	if (!strncasecmp(str, "lq057q3dc02", 11)) {
427		lpd270_lcd_to_use = &sharp_lq057q3dc02;
428	} else if (!strncasecmp(str, "lq121s1dg31", 11)) {
429		lpd270_lcd_to_use = &sharp_lq121s1dg31;
430	} else if (!strncasecmp(str, "lq036q1da01", 11)) {
431		lpd270_lcd_to_use = &sharp_lq036q1da01;
432	} else if (!strncasecmp(str, "lq64d343", 8)) {
433		lpd270_lcd_to_use = &sharp_lq64d343;
434	} else if (!strncasecmp(str, "lq10d368", 8)) {
435		lpd270_lcd_to_use = &sharp_lq10d368;
436	} else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
437		lpd270_lcd_to_use = &sharp_lq035q7db02_20;
438	} else {
439		printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
440	}
441
442	return 1;
443}
444
445__setup("lcd=", lpd270_set_lcd);
446
447static struct platform_device *platform_devices[] __initdata = {
448	&smc91x_device,
449	&lpd270_backlight_device,
450	&lpd270_flash_device[0],
451	&lpd270_flash_device[1],
452};
453
454static struct pxaohci_platform_data lpd270_ohci_platform_data = {
455	.port_mode	= PMM_PERPORT_MODE,
456	.flags		= ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
457};
458
459static void __init lpd270_init(void)
460{
461	pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
462
463	pxa_set_ffuart_info(NULL);
464	pxa_set_btuart_info(NULL);
465	pxa_set_stuart_info(NULL);
466
467	lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
468	lpd270_flash_data[1].width = 4;
469
470	/*
471	 * System bus arbiter setting:
472	 * - Core_Park
473	 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
474	 */
475	ARB_CNTRL = ARB_CORE_PARK | 0x234;
476
477	pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
478	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
479
480	pxa_set_ac97_info(NULL);
481
482	if (lpd270_lcd_to_use != NULL)
483		pxa_set_fb_info(NULL, lpd270_lcd_to_use);
484
485	pxa_set_ohci_info(&lpd270_ohci_platform_data);
486}
487
488
489static struct map_desc lpd270_io_desc[] __initdata = {
490	{
491		.virtual	= (unsigned long)LPD270_CPLD_VIRT,
492		.pfn		= __phys_to_pfn(LPD270_CPLD_PHYS),
493		.length		= LPD270_CPLD_SIZE,
494		.type		= MT_DEVICE,
495	},
496};
497
498static void __init lpd270_map_io(void)
499{
500	pxa27x_map_io();
501	iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
502
503	/* for use I SRAM as framebuffer.  */
504	PSLR |= 0x00000F04;
505	PCFR  = 0x00000066;
506}
507
508MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
509	/* Maintainer: Peter Barada */
510	.atag_offset	= 0x100,
511	.map_io		= lpd270_map_io,
512	.nr_irqs	= LPD270_NR_IRQS,
513	.init_irq	= lpd270_init_irq,
514	.handle_irq	= pxa27x_handle_irq,
515	.init_time	= pxa_timer_init,
516	.init_machine	= lpd270_init,
517	.restart	= pxa_restart,
518MACHINE_END
519