xref: /kernel/linux/linux-5.10/arch/arm/mach-pxa/idp.h (revision 8c2ecf20) 
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *  arch/arm/mach-pxa/include/mach/idp.h
4 *
5 * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
6 *
7 * 2001-09-13: Cliff Brake <cbrake@accelent.com>
8 *             Initial code
9 *
10 * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
11 *             <http://www.vibren.com> <http://bec-systems.com>
12 *             Changes for 2.6 kernel.
13 */
14
15
16/*
17 * Note: this file must be safe to include in assembly files
18 *
19 * Support for the Vibren PXA255 IDP requires rev04 or later
20 * IDP hardware.
21 */
22
23#include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
24
25#define IDP_FLASH_PHYS		(PXA_CS0_PHYS)
26#define IDP_ALT_FLASH_PHYS	(PXA_CS1_PHYS)
27#define IDP_MEDIAQ_PHYS		(PXA_CS3_PHYS)
28#define IDP_IDE_PHYS		(PXA_CS5_PHYS + 0x03000000)
29#define IDP_ETH_PHYS		(PXA_CS5_PHYS + 0x03400000)
30#define IDP_COREVOLT_PHYS	(PXA_CS5_PHYS + 0x03800000)
31#define IDP_CPLD_PHYS		(PXA_CS5_PHYS + 0x03C00000)
32
33
34/*
35 * virtual memory map
36 */
37
38#define IDP_COREVOLT_VIRT	(0xf0000000)
39#define IDP_COREVOLT_SIZE	(1*1024*1024)
40
41#define IDP_CPLD_VIRT		(IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
42#define IDP_CPLD_SIZE		(1*1024*1024)
43
44#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
45#error Your custom IO space is getting a bit large !!
46#endif
47
48#define CPLD_P2V(x)		((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
49#define CPLD_V2P(x)		((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
50
51#ifndef __ASSEMBLY__
52#  define __CPLD_REG(x)		(*((volatile unsigned long *)CPLD_P2V(x)))
53#else
54#  define __CPLD_REG(x)		CPLD_P2V(x)
55#endif
56
57/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
58
59#define _IDP_CPLD_REV			(IDP_CPLD_PHYS + 0x00)
60#define _IDP_CPLD_PERIPH_PWR		(IDP_CPLD_PHYS + 0x04)
61#define _IDP_CPLD_LED_CONTROL		(IDP_CPLD_PHYS + 0x08)
62#define _IDP_CPLD_KB_COL_HIGH		(IDP_CPLD_PHYS + 0x0C)
63#define _IDP_CPLD_KB_COL_LOW		(IDP_CPLD_PHYS + 0x10)
64#define _IDP_CPLD_PCCARD_EN		(IDP_CPLD_PHYS + 0x14)
65#define _IDP_CPLD_GPIOH_DIR		(IDP_CPLD_PHYS + 0x18)
66#define _IDP_CPLD_GPIOH_VALUE		(IDP_CPLD_PHYS + 0x1C)
67#define _IDP_CPLD_GPIOL_DIR		(IDP_CPLD_PHYS + 0x20)
68#define _IDP_CPLD_GPIOL_VALUE		(IDP_CPLD_PHYS + 0x24)
69#define _IDP_CPLD_PCCARD_PWR		(IDP_CPLD_PHYS + 0x28)
70#define _IDP_CPLD_MISC_CTRL		(IDP_CPLD_PHYS + 0x2C)
71#define _IDP_CPLD_LCD			(IDP_CPLD_PHYS + 0x30)
72#define _IDP_CPLD_FLASH_WE		(IDP_CPLD_PHYS + 0x34)
73
74#define _IDP_CPLD_KB_ROW		(IDP_CPLD_PHYS + 0x50)
75#define _IDP_CPLD_PCCARD0_STATUS	(IDP_CPLD_PHYS + 0x54)
76#define _IDP_CPLD_PCCARD1_STATUS	(IDP_CPLD_PHYS + 0x58)
77#define _IDP_CPLD_MISC_STATUS		(IDP_CPLD_PHYS + 0x5C)
78
79/* FPGA register virtual addresses */
80
81#define IDP_CPLD_REV			__CPLD_REG(_IDP_CPLD_REV)
82#define IDP_CPLD_PERIPH_PWR		__CPLD_REG(_IDP_CPLD_PERIPH_PWR)
83#define IDP_CPLD_LED_CONTROL		__CPLD_REG(_IDP_CPLD_LED_CONTROL)
84#define IDP_CPLD_KB_COL_HIGH		__CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
85#define IDP_CPLD_KB_COL_LOW		__CPLD_REG(_IDP_CPLD_KB_COL_LOW)
86#define IDP_CPLD_PCCARD_EN		__CPLD_REG(_IDP_CPLD_PCCARD_EN)
87#define IDP_CPLD_GPIOH_DIR		__CPLD_REG(_IDP_CPLD_GPIOH_DIR)
88#define IDP_CPLD_GPIOH_VALUE		__CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
89#define IDP_CPLD_GPIOL_DIR		__CPLD_REG(_IDP_CPLD_GPIOL_DIR)
90#define IDP_CPLD_GPIOL_VALUE		__CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
91#define IDP_CPLD_PCCARD_PWR		__CPLD_REG(_IDP_CPLD_PCCARD_PWR)
92#define IDP_CPLD_MISC_CTRL		__CPLD_REG(_IDP_CPLD_MISC_CTRL)
93#define IDP_CPLD_LCD			__CPLD_REG(_IDP_CPLD_LCD)
94#define IDP_CPLD_FLASH_WE		__CPLD_REG(_IDP_CPLD_FLASH_WE)
95
96#define IDP_CPLD_KB_ROW		        __CPLD_REG(_IDP_CPLD_KB_ROW)
97#define IDP_CPLD_PCCARD0_STATUS	        __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
98#define IDP_CPLD_PCCARD1_STATUS	        __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
99#define IDP_CPLD_MISC_STATUS		__CPLD_REG(_IDP_CPLD_MISC_STATUS)
100
101
102/*
103 * Bit masks for various registers
104 */
105
106// IDP_CPLD_PCCARD_PWR
107#define PCC0_PWR0	(1 << 0)
108#define PCC0_PWR1	(1 << 1)
109#define PCC0_PWR2	(1 << 2)
110#define PCC0_PWR3	(1 << 3)
111#define PCC1_PWR0	(1 << 4)
112#define PCC1_PWR1	(1 << 5)
113#define PCC1_PWR2	(1 << 6)
114#define PCC1_PWR3	(1 << 7)
115
116// IDP_CPLD_PCCARD_EN
117#define PCC0_RESET	(1 << 6)
118#define PCC1_RESET	(1 << 7)
119#define PCC0_ENABLE	(1 << 0)
120#define PCC1_ENABLE	(1 << 1)
121
122// IDP_CPLD_PCCARDx_STATUS
123#define _PCC_WRPROT	(1 << 7) // 7-4 read as low true
124#define _PCC_RESET	(1 << 6)
125#define _PCC_IRQ	(1 << 5)
126#define _PCC_INPACK	(1 << 4)
127#define PCC_BVD2	(1 << 3)
128#define PCC_BVD1	(1 << 2)
129#define PCC_VS2		(1 << 1)
130#define PCC_VS1		(1 << 0)
131
132/* A listing of interrupts used by external hardware devices */
133
134#define TOUCH_PANEL_IRQ			PXA_GPIO_TO_IRQ(5)
135#define IDE_IRQ				PXA_GPIO_TO_IRQ(21)
136
137#define TOUCH_PANEL_IRQ_EDGE		IRQ_TYPE_EDGE_FALLING
138
139#define ETHERNET_IRQ			PXA_GPIO_TO_IRQ(4)
140#define ETHERNET_IRQ_EDGE		IRQ_TYPE_EDGE_RISING
141
142#define IDE_IRQ_EDGE			IRQ_TYPE_EDGE_RISING
143
144#define PCMCIA_S0_CD_VALID		PXA_GPIO_TO_IRQ(7)
145#define PCMCIA_S0_CD_VALID_EDGE		IRQ_TYPE_EDGE_BOTH
146
147#define PCMCIA_S1_CD_VALID		PXA_GPIO_TO_IRQ(8)
148#define PCMCIA_S1_CD_VALID_EDGE		IRQ_TYPE_EDGE_BOTH
149
150#define PCMCIA_S0_RDYINT		PXA_GPIO_TO_IRQ(19)
151#define PCMCIA_S1_RDYINT		PXA_GPIO_TO_IRQ(22)
152
153
154/*
155 * Macros for LED Driver
156 */
157
158/* leds 0 = ON */
159#define IDP_HB_LED	(1<<5)
160#define IDP_BUSY_LED	(1<<6)
161
162#define IDP_LEDS_MASK	(IDP_HB_LED | IDP_BUSY_LED)
163
164/*
165 * macros for MTD driver
166 */
167
168#define FLASH_WRITE_PROTECT_DISABLE()	((IDP_CPLD_FLASH_WE) &= ~(0x1))
169#define FLASH_WRITE_PROTECT_ENABLE()	((IDP_CPLD_FLASH_WE) |= (0x1))
170
171/*
172 * macros for matrix keyboard driver
173 */
174
175#define KEYBD_MATRIX_NUMBER_INPUTS	7
176#define KEYBD_MATRIX_NUMBER_OUTPUTS	14
177
178#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC	FALSE
179#define KEYBD_MATRIX_INVERT_INPUT_LOGIC		FALSE
180
181#define KEYBD_MATRIX_SETTLING_TIME_US			100
182#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT		2
183
184#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
185{\
186	IDP_CPLD_KB_COL_LOW = outputs;\
187	IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
188}
189
190#define KEYBD_MATRIX_GET_INPUTS(inputs) \
191{\
192	inputs = (IDP_CPLD_KB_ROW & 0x7f);\
193}
194
195
196