18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com> 48c2ecf20Sopenharmony_ci * Copyright (c) 2003 ARM Limited 58c2ecf20Sopenharmony_ci * All Rights Reserved 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci#include <linux/linkage.h> 88c2ecf20Sopenharmony_ci#include <linux/init.h> 98c2ecf20Sopenharmony_ci 108c2ecf20Sopenharmony_ci __INIT 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci/* 138c2ecf20Sopenharmony_ci * OX820 specific entry point for secondary CPUs. 148c2ecf20Sopenharmony_ci */ 158c2ecf20Sopenharmony_ciENTRY(ox820_secondary_startup) 168c2ecf20Sopenharmony_ci mov r4, #0 178c2ecf20Sopenharmony_ci /* invalidate both caches and branch target cache */ 188c2ecf20Sopenharmony_ci mcr p15, 0, r4, c7, c7, 0 198c2ecf20Sopenharmony_ci /* 208c2ecf20Sopenharmony_ci * we've been released from the holding pen: secondary_stack 218c2ecf20Sopenharmony_ci * should now contain the SVC stack for this core 228c2ecf20Sopenharmony_ci */ 238c2ecf20Sopenharmony_ci b secondary_startup 24