18c2ecf20Sopenharmony_ci/*
28c2ecf20Sopenharmony_ci * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
38c2ecf20Sopenharmony_ci *
48c2ecf20Sopenharmony_ci * Marvell Orion-VoIP GE Reference Design Setup
58c2ecf20Sopenharmony_ci *
68c2ecf20Sopenharmony_ci * This file is licensed under the terms of the GNU General Public
78c2ecf20Sopenharmony_ci * License version 2.  This program is licensed "as is" without any
88c2ecf20Sopenharmony_ci * warranty of any kind, whether express or implied.
98c2ecf20Sopenharmony_ci */
108c2ecf20Sopenharmony_ci#include <linux/gpio.h>
118c2ecf20Sopenharmony_ci#include <linux/kernel.h>
128c2ecf20Sopenharmony_ci#include <linux/init.h>
138c2ecf20Sopenharmony_ci#include <linux/platform_device.h>
148c2ecf20Sopenharmony_ci#include <linux/pci.h>
158c2ecf20Sopenharmony_ci#include <linux/irq.h>
168c2ecf20Sopenharmony_ci#include <linux/mtd/physmap.h>
178c2ecf20Sopenharmony_ci#include <linux/mv643xx_eth.h>
188c2ecf20Sopenharmony_ci#include <linux/ethtool.h>
198c2ecf20Sopenharmony_ci#include <linux/i2c.h>
208c2ecf20Sopenharmony_ci#include <linux/platform_data/dsa.h>
218c2ecf20Sopenharmony_ci#include <asm/mach-types.h>
228c2ecf20Sopenharmony_ci#include <asm/mach/arch.h>
238c2ecf20Sopenharmony_ci#include <asm/mach/pci.h>
248c2ecf20Sopenharmony_ci#include "common.h"
258c2ecf20Sopenharmony_ci#include "mpp.h"
268c2ecf20Sopenharmony_ci#include "orion5x.h"
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci/*****************************************************************************
298c2ecf20Sopenharmony_ci * RD-88F5181L GE Info
308c2ecf20Sopenharmony_ci ****************************************************************************/
318c2ecf20Sopenharmony_ci/*
328c2ecf20Sopenharmony_ci * 16M NOR flash Device bus boot chip select
338c2ecf20Sopenharmony_ci */
348c2ecf20Sopenharmony_ci#define RD88F5181L_GE_NOR_BOOT_BASE		0xff000000
358c2ecf20Sopenharmony_ci#define RD88F5181L_GE_NOR_BOOT_SIZE		SZ_16M
368c2ecf20Sopenharmony_ci
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ci/*****************************************************************************
398c2ecf20Sopenharmony_ci * 16M NOR Flash on Device bus Boot chip select
408c2ecf20Sopenharmony_ci ****************************************************************************/
418c2ecf20Sopenharmony_cistatic struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = {
428c2ecf20Sopenharmony_ci	.width		= 1,
438c2ecf20Sopenharmony_ci};
448c2ecf20Sopenharmony_ci
458c2ecf20Sopenharmony_cistatic struct resource rd88f5181l_ge_nor_boot_flash_resource = {
468c2ecf20Sopenharmony_ci	.flags		= IORESOURCE_MEM,
478c2ecf20Sopenharmony_ci	.start		= RD88F5181L_GE_NOR_BOOT_BASE,
488c2ecf20Sopenharmony_ci	.end		= RD88F5181L_GE_NOR_BOOT_BASE +
498c2ecf20Sopenharmony_ci			  RD88F5181L_GE_NOR_BOOT_SIZE - 1,
508c2ecf20Sopenharmony_ci};
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_cistatic struct platform_device rd88f5181l_ge_nor_boot_flash = {
538c2ecf20Sopenharmony_ci	.name			= "physmap-flash",
548c2ecf20Sopenharmony_ci	.id			= 0,
558c2ecf20Sopenharmony_ci	.dev		= {
568c2ecf20Sopenharmony_ci		.platform_data	= &rd88f5181l_ge_nor_boot_flash_data,
578c2ecf20Sopenharmony_ci	},
588c2ecf20Sopenharmony_ci	.num_resources		= 1,
598c2ecf20Sopenharmony_ci	.resource		= &rd88f5181l_ge_nor_boot_flash_resource,
608c2ecf20Sopenharmony_ci};
618c2ecf20Sopenharmony_ci
628c2ecf20Sopenharmony_ci
638c2ecf20Sopenharmony_ci/*****************************************************************************
648c2ecf20Sopenharmony_ci * General Setup
658c2ecf20Sopenharmony_ci ****************************************************************************/
668c2ecf20Sopenharmony_cistatic unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
678c2ecf20Sopenharmony_ci	MPP0_GPIO,		/* LED1 */
688c2ecf20Sopenharmony_ci	MPP1_GPIO,		/* LED5 */
698c2ecf20Sopenharmony_ci	MPP2_GPIO,		/* LED4 */
708c2ecf20Sopenharmony_ci	MPP3_GPIO,		/* LED3 */
718c2ecf20Sopenharmony_ci	MPP4_GPIO,		/* PCI_intA */
728c2ecf20Sopenharmony_ci	MPP5_GPIO,		/* RTC interrupt */
738c2ecf20Sopenharmony_ci	MPP6_PCI_CLK,		/* CPU PCI refclk */
748c2ecf20Sopenharmony_ci	MPP7_PCI_CLK,		/* PCI/PCIe refclk */
758c2ecf20Sopenharmony_ci	MPP8_GPIO,		/* 88e6131 interrupt */
768c2ecf20Sopenharmony_ci	MPP9_GPIO,		/* GE_RXERR */
778c2ecf20Sopenharmony_ci	MPP10_GPIO,		/* PCI_intB */
788c2ecf20Sopenharmony_ci	MPP11_GPIO,		/* LED2 */
798c2ecf20Sopenharmony_ci	MPP12_GIGE,		/* GE_TXD[4] */
808c2ecf20Sopenharmony_ci	MPP13_GIGE,		/* GE_TXD[5] */
818c2ecf20Sopenharmony_ci	MPP14_GIGE,		/* GE_TXD[6] */
828c2ecf20Sopenharmony_ci	MPP15_GIGE,		/* GE_TXD[7] */
838c2ecf20Sopenharmony_ci	MPP16_GIGE,		/* GE_RXD[4] */
848c2ecf20Sopenharmony_ci	MPP17_GIGE,		/* GE_RXD[5] */
858c2ecf20Sopenharmony_ci	MPP18_GIGE,		/* GE_RXD[6] */
868c2ecf20Sopenharmony_ci	MPP19_GIGE,		/* GE_RXD[7] */
878c2ecf20Sopenharmony_ci	0,
888c2ecf20Sopenharmony_ci};
898c2ecf20Sopenharmony_ci
908c2ecf20Sopenharmony_cistatic struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
918c2ecf20Sopenharmony_ci	.phy_addr	= MV643XX_ETH_PHY_NONE,
928c2ecf20Sopenharmony_ci	.speed		= SPEED_1000,
938c2ecf20Sopenharmony_ci	.duplex		= DUPLEX_FULL,
948c2ecf20Sopenharmony_ci};
958c2ecf20Sopenharmony_ci
968c2ecf20Sopenharmony_cistatic struct dsa_chip_data rd88f5181l_ge_switch_chip_data = {
978c2ecf20Sopenharmony_ci	.port_names[0]	= "lan2",
988c2ecf20Sopenharmony_ci	.port_names[1]	= "lan1",
998c2ecf20Sopenharmony_ci	.port_names[2]	= "wan",
1008c2ecf20Sopenharmony_ci	.port_names[3]	= "cpu",
1018c2ecf20Sopenharmony_ci	.port_names[5]	= "lan4",
1028c2ecf20Sopenharmony_ci	.port_names[7]	= "lan3",
1038c2ecf20Sopenharmony_ci};
1048c2ecf20Sopenharmony_ci
1058c2ecf20Sopenharmony_cistatic struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
1068c2ecf20Sopenharmony_ci	I2C_BOARD_INFO("ds1338", 0x68),
1078c2ecf20Sopenharmony_ci};
1088c2ecf20Sopenharmony_ci
1098c2ecf20Sopenharmony_cistatic void __init rd88f5181l_ge_init(void)
1108c2ecf20Sopenharmony_ci{
1118c2ecf20Sopenharmony_ci	/*
1128c2ecf20Sopenharmony_ci	 * Setup basic Orion functions. Need to be called early.
1138c2ecf20Sopenharmony_ci	 */
1148c2ecf20Sopenharmony_ci	orion5x_init();
1158c2ecf20Sopenharmony_ci
1168c2ecf20Sopenharmony_ci	orion5x_mpp_conf(rd88f5181l_ge_mpp_modes);
1178c2ecf20Sopenharmony_ci
1188c2ecf20Sopenharmony_ci	/*
1198c2ecf20Sopenharmony_ci	 * Configure peripherals.
1208c2ecf20Sopenharmony_ci	 */
1218c2ecf20Sopenharmony_ci	orion5x_ehci0_init();
1228c2ecf20Sopenharmony_ci	orion5x_eth_init(&rd88f5181l_ge_eth_data);
1238c2ecf20Sopenharmony_ci	orion5x_eth_switch_init(&rd88f5181l_ge_switch_chip_data);
1248c2ecf20Sopenharmony_ci	orion5x_i2c_init();
1258c2ecf20Sopenharmony_ci	orion5x_uart0_init();
1268c2ecf20Sopenharmony_ci
1278c2ecf20Sopenharmony_ci	mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
1288c2ecf20Sopenharmony_ci				    ORION_MBUS_DEVBUS_BOOT_ATTR,
1298c2ecf20Sopenharmony_ci				    RD88F5181L_GE_NOR_BOOT_BASE,
1308c2ecf20Sopenharmony_ci				    RD88F5181L_GE_NOR_BOOT_SIZE);
1318c2ecf20Sopenharmony_ci	platform_device_register(&rd88f5181l_ge_nor_boot_flash);
1328c2ecf20Sopenharmony_ci
1338c2ecf20Sopenharmony_ci	i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
1348c2ecf20Sopenharmony_ci}
1358c2ecf20Sopenharmony_ci
1368c2ecf20Sopenharmony_cistatic int __init
1378c2ecf20Sopenharmony_cird88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1388c2ecf20Sopenharmony_ci{
1398c2ecf20Sopenharmony_ci	int irq;
1408c2ecf20Sopenharmony_ci
1418c2ecf20Sopenharmony_ci	/*
1428c2ecf20Sopenharmony_ci	 * Check for devices with hard-wired IRQs.
1438c2ecf20Sopenharmony_ci	 */
1448c2ecf20Sopenharmony_ci	irq = orion5x_pci_map_irq(dev, slot, pin);
1458c2ecf20Sopenharmony_ci	if (irq != -1)
1468c2ecf20Sopenharmony_ci		return irq;
1478c2ecf20Sopenharmony_ci
1488c2ecf20Sopenharmony_ci	/*
1498c2ecf20Sopenharmony_ci	 * Cardbus slot.
1508c2ecf20Sopenharmony_ci	 */
1518c2ecf20Sopenharmony_ci	if (pin == 1)
1528c2ecf20Sopenharmony_ci		return gpio_to_irq(4);
1538c2ecf20Sopenharmony_ci	else
1548c2ecf20Sopenharmony_ci		return gpio_to_irq(10);
1558c2ecf20Sopenharmony_ci}
1568c2ecf20Sopenharmony_ci
1578c2ecf20Sopenharmony_cistatic struct hw_pci rd88f5181l_ge_pci __initdata = {
1588c2ecf20Sopenharmony_ci	.nr_controllers	= 2,
1598c2ecf20Sopenharmony_ci	.setup		= orion5x_pci_sys_setup,
1608c2ecf20Sopenharmony_ci	.scan		= orion5x_pci_sys_scan_bus,
1618c2ecf20Sopenharmony_ci	.map_irq	= rd88f5181l_ge_pci_map_irq,
1628c2ecf20Sopenharmony_ci};
1638c2ecf20Sopenharmony_ci
1648c2ecf20Sopenharmony_cistatic int __init rd88f5181l_ge_pci_init(void)
1658c2ecf20Sopenharmony_ci{
1668c2ecf20Sopenharmony_ci	if (machine_is_rd88f5181l_ge()) {
1678c2ecf20Sopenharmony_ci		orion5x_pci_set_cardbus_mode();
1688c2ecf20Sopenharmony_ci		pci_common_init(&rd88f5181l_ge_pci);
1698c2ecf20Sopenharmony_ci	}
1708c2ecf20Sopenharmony_ci
1718c2ecf20Sopenharmony_ci	return 0;
1728c2ecf20Sopenharmony_ci}
1738c2ecf20Sopenharmony_cisubsys_initcall(rd88f5181l_ge_pci_init);
1748c2ecf20Sopenharmony_ci
1758c2ecf20Sopenharmony_ciMACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
1768c2ecf20Sopenharmony_ci	/* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
1778c2ecf20Sopenharmony_ci	.atag_offset	= 0x100,
1788c2ecf20Sopenharmony_ci	.nr_irqs	= ORION5X_NR_IRQS,
1798c2ecf20Sopenharmony_ci	.init_machine	= rd88f5181l_ge_init,
1808c2ecf20Sopenharmony_ci	.map_io		= orion5x_map_io,
1818c2ecf20Sopenharmony_ci	.init_early	= orion5x_init_early,
1828c2ecf20Sopenharmony_ci	.init_irq	= orion5x_init_irq,
1838c2ecf20Sopenharmony_ci	.init_time	= orion5x_timer_init,
1848c2ecf20Sopenharmony_ci	.fixup		= tag_fixup_mem32,
1858c2ecf20Sopenharmony_ci	.restart	= orion5x_restart,
1868c2ecf20Sopenharmony_ciMACHINE_END
187