18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Interface for functions that need to be run in internal SRAM 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#ifndef __ASSEMBLY__ 78c2ecf20Sopenharmony_ci#include <plat/sram.h> 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciextern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 108c2ecf20Sopenharmony_ci u32 base_cs, u32 force_unlock); 118c2ecf20Sopenharmony_ciextern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, 128c2ecf20Sopenharmony_ci u32 mem_type); 138c2ecf20Sopenharmony_ciextern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciextern void omap3_sram_restore_context(void); 168c2ecf20Sopenharmony_ci 178c2ecf20Sopenharmony_ci/* Do not use these */ 188c2ecf20Sopenharmony_ciextern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 198c2ecf20Sopenharmony_ciextern unsigned long omap24xx_sram_reprogram_clock_sz; 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ciextern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 228c2ecf20Sopenharmony_ci u32 base_cs, u32 force_unlock); 238c2ecf20Sopenharmony_ciextern unsigned long omap242x_sram_ddr_init_sz; 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ciextern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, 268c2ecf20Sopenharmony_ci int bypass); 278c2ecf20Sopenharmony_ciextern unsigned long omap242x_sram_set_prcm_sz; 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ciextern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, 308c2ecf20Sopenharmony_ci u32 mem_type); 318c2ecf20Sopenharmony_ciextern unsigned long omap242x_sram_reprogram_sdrc_sz; 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ciextern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 358c2ecf20Sopenharmony_ci u32 base_cs, u32 force_unlock); 368c2ecf20Sopenharmony_ciextern unsigned long omap243x_sram_ddr_init_sz; 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ciextern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, 398c2ecf20Sopenharmony_ci int bypass); 408c2ecf20Sopenharmony_ciextern unsigned long omap243x_sram_set_prcm_sz; 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ciextern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, 438c2ecf20Sopenharmony_ci u32 mem_type); 448c2ecf20Sopenharmony_ciextern unsigned long omap243x_sram_reprogram_sdrc_sz; 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ci#ifdef CONFIG_PM 478c2ecf20Sopenharmony_ciextern void omap_push_sram_idle(void); 488c2ecf20Sopenharmony_ci#else 498c2ecf20Sopenharmony_cistatic inline void omap_push_sram_idle(void) {} 508c2ecf20Sopenharmony_ci#endif /* CONFIG_PM */ 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#endif /* __ASSEMBLY__ */ 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci/* 558c2ecf20Sopenharmony_ci * OMAP2+: define the SRAM PA addresses. 568c2ecf20Sopenharmony_ci * Used by the SRAM management code and the idle sleep code. 578c2ecf20Sopenharmony_ci */ 588c2ecf20Sopenharmony_ci#define OMAP2_SRAM_PA 0x40200000 598c2ecf20Sopenharmony_ci#define OMAP3_SRAM_PA 0x40200000 60