1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * OMAP54XX SCRM registers and bitfields 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Benoit Cousson (b-cousson@ti.com) 8 * 9 * This file is automatically generated from the OMAP hardware databases. 10 * We respectfully ask that any modifications to this file be coordinated 11 * with the public linux-omap@vger.kernel.org mailing list and the 12 * authors above to ensure that the autogeneration scripts are kept 13 * up-to-date with the file contents. 14 */ 15 16#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H 17#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H 18 19#define OMAP5_SCRM_BASE 0x4ae0a000 20 21#define OMAP54XX_SCRM_REGADDR(reg) \ 22 OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg)) 23 24/* SCRM */ 25 26/* SCRM.SCRM register offsets */ 27#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000 28#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000) 29#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100 30#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100) 31#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104 32#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104) 33#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110 34#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110) 35#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118 36#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118) 37#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c 38#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c) 39#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200 40#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200) 41#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204 42#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204) 43#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208 44#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208) 45#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210 46#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210) 47#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214 48#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214) 49#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218 50#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218) 51#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c 52#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c) 53#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220 54#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220) 55#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224 56#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224) 57#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234 58#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234) 59#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310 60#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310) 61#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314 62#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314) 63#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318 64#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318) 65#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c 66#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c) 67#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320 68#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320) 69#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324 70#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324) 71#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400 72#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400) 73#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418 74#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418) 75#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c 76#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c) 77#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 78#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420) 79#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510 80#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510) 81#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514 82#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514) 83#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518 84#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518) 85#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c 86#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c) 87 88/* 89 * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, 90 * AUXCLKREQ5, D2DCLKREQ 91 */ 92#define OMAP5_ACCURACY_SHIFT 1 93#define OMAP5_ACCURACY_WIDTH 0x1 94#define OMAP5_ACCURACY_MASK (1 << 1) 95 96/* Used by APEWARMRSTST */ 97#define OMAP5_APEWARMRSTST_SHIFT 1 98#define OMAP5_APEWARMRSTST_WIDTH 0x1 99#define OMAP5_APEWARMRSTST_MASK (1 << 1) 100 101/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ 102#define OMAP5_CLKDIV_SHIFT 16 103#define OMAP5_CLKDIV_WIDTH 0x4 104#define OMAP5_CLKDIV_MASK (0xf << 16) 105 106/* Used by D2DCLKM, MODEMCLKM */ 107#define OMAP5_CLK_32KHZ_SHIFT 0 108#define OMAP5_CLK_32KHZ_WIDTH 0x1 109#define OMAP5_CLK_32KHZ_MASK (1 << 0) 110 111/* Used by D2DRSTCTRL, MODEMRSTCTRL */ 112#define OMAP5_COLDRST_SHIFT 0 113#define OMAP5_COLDRST_WIDTH 0x1 114#define OMAP5_COLDRST_MASK (1 << 0) 115 116/* Used by D2DWARMRSTST */ 117#define OMAP5_D2DWARMRSTST_SHIFT 3 118#define OMAP5_D2DWARMRSTST_WIDTH 0x1 119#define OMAP5_D2DWARMRSTST_MASK (1 << 3) 120 121/* Used by AUXCLK0 */ 122#define OMAP5_DISABLECLK_SHIFT 9 123#define OMAP5_DISABLECLK_WIDTH 0x1 124#define OMAP5_DISABLECLK_MASK (1 << 9) 125 126/* Used by CLKSETUPTIME */ 127#define OMAP5_DOWNTIME_SHIFT 16 128#define OMAP5_DOWNTIME_WIDTH 0x6 129#define OMAP5_DOWNTIME_MASK (0x3f << 16) 130 131/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ 132#define OMAP5_ENABLE_SHIFT 8 133#define OMAP5_ENABLE_WIDTH 0x1 134#define OMAP5_ENABLE_MASK (1 << 8) 135 136/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */ 137#define OMAP5_ENABLE_0_0_SHIFT 0 138#define OMAP5_ENABLE_0_0_WIDTH 0x1 139#define OMAP5_ENABLE_0_0_MASK (1 << 0) 140 141/* Used by ALTCLKSRC */ 142#define OMAP5_ENABLE_EXT_SHIFT 3 143#define OMAP5_ENABLE_EXT_WIDTH 0x1 144#define OMAP5_ENABLE_EXT_MASK (1 << 3) 145 146/* Used by ALTCLKSRC */ 147#define OMAP5_ENABLE_INT_SHIFT 2 148#define OMAP5_ENABLE_INT_WIDTH 0x1 149#define OMAP5_ENABLE_INT_MASK (1 << 2) 150 151/* Used by EXTWARMRSTST */ 152#define OMAP5_EXTWARMRSTST_SHIFT 0 153#define OMAP5_EXTWARMRSTST_WIDTH 0x1 154#define OMAP5_EXTWARMRSTST_MASK (1 << 0) 155 156/* 157 * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, 158 * AUXCLKREQ5 159 */ 160#define OMAP5_MAPPING_SHIFT 2 161#define OMAP5_MAPPING_WIDTH 0x3 162#define OMAP5_MAPPING_MASK (0x7 << 2) 163 164/* Used by ALTCLKSRC */ 165#define OMAP5_MODE_SHIFT 0 166#define OMAP5_MODE_WIDTH 0x2 167#define OMAP5_MODE_MASK (0x3 << 0) 168 169/* Used by MODEMWARMRSTST */ 170#define OMAP5_MODEMWARMRSTST_SHIFT 2 171#define OMAP5_MODEMWARMRSTST_WIDTH 0x1 172#define OMAP5_MODEMWARMRSTST_MASK (1 << 2) 173 174/* 175 * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5, 176 * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5, 177 * D2DCLKREQ, EXTCLKREQ, PWRREQ 178 */ 179#define OMAP5_POLARITY_SHIFT 0 180#define OMAP5_POLARITY_WIDTH 0x1 181#define OMAP5_POLARITY_MASK (1 << 0) 182 183/* Used by EXTPWRONRSTCTRL */ 184#define OMAP5_PWRONRST_SHIFT 1 185#define OMAP5_PWRONRST_WIDTH 0x1 186#define OMAP5_PWRONRST_MASK (1 << 1) 187 188/* Used by REVISION_SCRM */ 189#define OMAP5_REV_SHIFT 0 190#define OMAP5_REV_WIDTH 0x8 191#define OMAP5_REV_MASK (0xff << 0) 192 193/* Used by RSTTIME */ 194#define OMAP5_RSTTIME_SHIFT 0 195#define OMAP5_RSTTIME_WIDTH 0x4 196#define OMAP5_RSTTIME_MASK (0xf << 0) 197 198/* Used by CLKSETUPTIME */ 199#define OMAP5_SETUPTIME_SHIFT 0 200#define OMAP5_SETUPTIME_WIDTH 0xc 201#define OMAP5_SETUPTIME_MASK (0xfff << 0) 202 203/* Used by PMICSETUPTIME */ 204#define OMAP5_SLEEPTIME_SHIFT 0 205#define OMAP5_SLEEPTIME_WIDTH 0x6 206#define OMAP5_SLEEPTIME_MASK (0x3f << 0) 207 208/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ 209#define OMAP5_SRCSELECT_SHIFT 1 210#define OMAP5_SRCSELECT_WIDTH 0x2 211#define OMAP5_SRCSELECT_MASK (0x3 << 1) 212 213/* Used by D2DCLKM */ 214#define OMAP5_SYSCLK_SHIFT 1 215#define OMAP5_SYSCLK_WIDTH 0x1 216#define OMAP5_SYSCLK_MASK (1 << 1) 217 218/* Used by PMICSETUPTIME */ 219#define OMAP5_WAKEUPTIME_SHIFT 16 220#define OMAP5_WAKEUPTIME_WIDTH 0x6 221#define OMAP5_WAKEUPTIME_MASK (0x3f << 16) 222 223/* Used by D2DRSTCTRL, MODEMRSTCTRL */ 224#define OMAP5_WARMRST_SHIFT 1 225#define OMAP5_WARMRST_WIDTH 0x1 226#define OMAP5_WARMRST_MASK (1 << 1) 227 228#endif 229