1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Hardware modules present on the DRA7xx chips 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Paul Walmsley 8 * Benoit Cousson 9 * 10 * This file is automatically generated from the OMAP hardware databases. 11 * We respectfully ask that any modifications to this file be coordinated 12 * with the public linux-omap@vger.kernel.org mailing list and the 13 * authors above to ensure that the autogeneration scripts are kept 14 * up-to-date with the file contents. 15 */ 16 17#include <linux/io.h> 18 19#include "omap_hwmod.h" 20#include "omap_hwmod_common_data.h" 21#include "cm1_7xx.h" 22#include "cm2_7xx.h" 23#include "prm7xx.h" 24#include "soc.h" 25 26/* Base offset for all DRA7XX interrupts external to MPUSS */ 27#define DRA7XX_IRQ_GIC_START 32 28 29/* 30 * IP blocks 31 */ 32 33/* 34 * 'dmm' class 35 * instance(s): dmm 36 */ 37static struct omap_hwmod_class dra7xx_dmm_hwmod_class = { 38 .name = "dmm", 39}; 40 41/* dmm */ 42static struct omap_hwmod dra7xx_dmm_hwmod = { 43 .name = "dmm", 44 .class = &dra7xx_dmm_hwmod_class, 45 .clkdm_name = "emif_clkdm", 46 .prcm = { 47 .omap4 = { 48 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET, 49 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET, 50 }, 51 }, 52}; 53 54/* 55 * 'l3' class 56 * instance(s): l3_instr, l3_main_1, l3_main_2 57 */ 58static struct omap_hwmod_class dra7xx_l3_hwmod_class = { 59 .name = "l3", 60}; 61 62/* l3_instr */ 63static struct omap_hwmod dra7xx_l3_instr_hwmod = { 64 .name = "l3_instr", 65 .class = &dra7xx_l3_hwmod_class, 66 .clkdm_name = "l3instr_clkdm", 67 .prcm = { 68 .omap4 = { 69 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, 70 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, 71 .modulemode = MODULEMODE_HWCTRL, 72 }, 73 }, 74}; 75 76/* l3_main_1 */ 77static struct omap_hwmod dra7xx_l3_main_1_hwmod = { 78 .name = "l3_main_1", 79 .class = &dra7xx_l3_hwmod_class, 80 .clkdm_name = "l3main1_clkdm", 81 .prcm = { 82 .omap4 = { 83 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET, 84 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET, 85 }, 86 }, 87}; 88 89/* l3_main_2 */ 90static struct omap_hwmod dra7xx_l3_main_2_hwmod = { 91 .name = "l3_main_2", 92 .class = &dra7xx_l3_hwmod_class, 93 .clkdm_name = "l3instr_clkdm", 94 .prcm = { 95 .omap4 = { 96 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET, 97 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET, 98 .modulemode = MODULEMODE_HWCTRL, 99 }, 100 }, 101}; 102 103/* 104 * 'l4' class 105 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup 106 */ 107static struct omap_hwmod_class dra7xx_l4_hwmod_class = { 108 .name = "l4", 109}; 110 111/* l4_cfg */ 112static struct omap_hwmod dra7xx_l4_cfg_hwmod = { 113 .name = "l4_cfg", 114 .class = &dra7xx_l4_hwmod_class, 115 .clkdm_name = "l4cfg_clkdm", 116 .prcm = { 117 .omap4 = { 118 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, 119 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, 120 }, 121 }, 122}; 123 124/* l4_per1 */ 125static struct omap_hwmod dra7xx_l4_per1_hwmod = { 126 .name = "l4_per1", 127 .class = &dra7xx_l4_hwmod_class, 128 .clkdm_name = "l4per_clkdm", 129 .prcm = { 130 .omap4 = { 131 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET, 132 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 133 }, 134 }, 135}; 136 137/* l4_per2 */ 138static struct omap_hwmod dra7xx_l4_per2_hwmod = { 139 .name = "l4_per2", 140 .class = &dra7xx_l4_hwmod_class, 141 .clkdm_name = "l4per2_clkdm", 142 .prcm = { 143 .omap4 = { 144 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET, 145 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 146 }, 147 }, 148}; 149 150/* l4_per3 */ 151static struct omap_hwmod dra7xx_l4_per3_hwmod = { 152 .name = "l4_per3", 153 .class = &dra7xx_l4_hwmod_class, 154 .clkdm_name = "l4per3_clkdm", 155 .prcm = { 156 .omap4 = { 157 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET, 158 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 159 }, 160 }, 161}; 162 163/* l4_wkup */ 164static struct omap_hwmod dra7xx_l4_wkup_hwmod = { 165 .name = "l4_wkup", 166 .class = &dra7xx_l4_hwmod_class, 167 .clkdm_name = "wkupaon_clkdm", 168 .prcm = { 169 .omap4 = { 170 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET, 171 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET, 172 }, 173 }, 174}; 175 176/* 177 * 'atl' class 178 * 179 */ 180 181static struct omap_hwmod_class dra7xx_atl_hwmod_class = { 182 .name = "atl", 183}; 184 185/* atl */ 186static struct omap_hwmod dra7xx_atl_hwmod = { 187 .name = "atl", 188 .class = &dra7xx_atl_hwmod_class, 189 .clkdm_name = "atl_clkdm", 190 .main_clk = "atl_gfclk_mux", 191 .prcm = { 192 .omap4 = { 193 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET, 194 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET, 195 .modulemode = MODULEMODE_SWCTRL, 196 }, 197 }, 198}; 199 200/* 201 * 'bb2d' class 202 * 203 */ 204 205static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = { 206 .name = "bb2d", 207}; 208 209/* bb2d */ 210static struct omap_hwmod dra7xx_bb2d_hwmod = { 211 .name = "bb2d", 212 .class = &dra7xx_bb2d_hwmod_class, 213 .clkdm_name = "dss_clkdm", 214 .main_clk = "dpll_core_h24x2_ck", 215 .prcm = { 216 .omap4 = { 217 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET, 218 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET, 219 .modulemode = MODULEMODE_SWCTRL, 220 }, 221 }, 222}; 223 224/* 225 * 'ctrl_module' class 226 * 227 */ 228 229static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = { 230 .name = "ctrl_module", 231}; 232 233/* ctrl_module_wkup */ 234static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { 235 .name = "ctrl_module_wkup", 236 .class = &dra7xx_ctrl_module_hwmod_class, 237 .clkdm_name = "wkupaon_clkdm", 238 .prcm = { 239 .omap4 = { 240 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, 241 }, 242 }, 243}; 244 245/* 246 * 'gpmc' class 247 * 248 */ 249 250static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = { 251 .rev_offs = 0x0000, 252 .sysc_offs = 0x0010, 253 .syss_offs = 0x0014, 254 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 255 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 256 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 257 .sysc_fields = &omap_hwmod_sysc_type1, 258}; 259 260static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = { 261 .name = "gpmc", 262 .sysc = &dra7xx_gpmc_sysc, 263}; 264 265/* gpmc */ 266 267static struct omap_hwmod dra7xx_gpmc_hwmod = { 268 .name = "gpmc", 269 .class = &dra7xx_gpmc_hwmod_class, 270 .clkdm_name = "l3main1_clkdm", 271 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 272 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, 273 .main_clk = "l3_iclk_div", 274 .prcm = { 275 .omap4 = { 276 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET, 277 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET, 278 .modulemode = MODULEMODE_HWCTRL, 279 }, 280 }, 281}; 282 283 284 285/* 286 * 'mpu' class 287 * 288 */ 289 290static struct omap_hwmod_class dra7xx_mpu_hwmod_class = { 291 .name = "mpu", 292}; 293 294/* mpu */ 295static struct omap_hwmod dra7xx_mpu_hwmod = { 296 .name = "mpu", 297 .class = &dra7xx_mpu_hwmod_class, 298 .clkdm_name = "mpu_clkdm", 299 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 300 .main_clk = "dpll_mpu_m2_ck", 301 .prcm = { 302 .omap4 = { 303 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET, 304 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET, 305 }, 306 }, 307}; 308 309 310/* 311 * 'PCIE' class 312 * 313 */ 314 315/* 316 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset 317 * functionality of OMAP HWMOD layer does not deassert the hardreset lines 318 * associated with an IP automatically leaving the driver to handle that 319 * by itself. This does not work for PCIeSS which needs the reset lines 320 * deasserted for the driver to start accessing registers. 321 * 322 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset 323 * lines after asserting them. 324 */ 325int dra7xx_pciess_reset(struct omap_hwmod *oh) 326{ 327 int i; 328 329 for (i = 0; i < oh->rst_lines_cnt; i++) { 330 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name); 331 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name); 332 } 333 334 return 0; 335} 336 337static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { 338 .name = "pcie", 339 .reset = dra7xx_pciess_reset, 340}; 341 342/* pcie1 */ 343static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = { 344 { .name = "pcie", .rst_shift = 0 }, 345}; 346 347static struct omap_hwmod dra7xx_pciess1_hwmod = { 348 .name = "pcie1", 349 .class = &dra7xx_pciess_hwmod_class, 350 .clkdm_name = "pcie_clkdm", 351 .rst_lines = dra7xx_pciess1_resets, 352 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets), 353 .main_clk = "l4_root_clk_div", 354 .prcm = { 355 .omap4 = { 356 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, 357 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, 358 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, 359 .modulemode = MODULEMODE_SWCTRL, 360 }, 361 }, 362}; 363 364/* pcie2 */ 365static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = { 366 { .name = "pcie", .rst_shift = 1 }, 367}; 368 369/* pcie2 */ 370static struct omap_hwmod dra7xx_pciess2_hwmod = { 371 .name = "pcie2", 372 .class = &dra7xx_pciess_hwmod_class, 373 .clkdm_name = "pcie_clkdm", 374 .rst_lines = dra7xx_pciess2_resets, 375 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets), 376 .main_clk = "l4_root_clk_div", 377 .prcm = { 378 .omap4 = { 379 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, 380 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, 381 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, 382 .modulemode = MODULEMODE_SWCTRL, 383 }, 384 }, 385}; 386 387/* 388 * 'qspi' class 389 * 390 */ 391 392static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = { 393 .rev_offs = 0, 394 .sysc_offs = 0x0010, 395 .sysc_flags = SYSC_HAS_SIDLEMODE, 396 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 397 SIDLE_SMART_WKUP), 398 .sysc_fields = &omap_hwmod_sysc_type2, 399}; 400 401static struct omap_hwmod_class dra7xx_qspi_hwmod_class = { 402 .name = "qspi", 403 .sysc = &dra7xx_qspi_sysc, 404}; 405 406/* qspi */ 407static struct omap_hwmod dra7xx_qspi_hwmod = { 408 .name = "qspi", 409 .class = &dra7xx_qspi_hwmod_class, 410 .clkdm_name = "l4per2_clkdm", 411 .main_clk = "qspi_gfclk_div", 412 .prcm = { 413 .omap4 = { 414 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET, 415 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET, 416 .modulemode = MODULEMODE_SWCTRL, 417 }, 418 }, 419}; 420 421/* 422 * 'sata' class 423 * 424 */ 425 426static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = { 427 .rev_offs = 0x00fc, 428 .sysc_offs = 0x0000, 429 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), 430 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 431 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 432 MSTANDBY_SMART | MSTANDBY_SMART_WKUP), 433 .sysc_fields = &omap_hwmod_sysc_type2, 434}; 435 436static struct omap_hwmod_class dra7xx_sata_hwmod_class = { 437 .name = "sata", 438 .sysc = &dra7xx_sata_sysc, 439}; 440 441/* sata */ 442 443static struct omap_hwmod dra7xx_sata_hwmod = { 444 .name = "sata", 445 .class = &dra7xx_sata_hwmod_class, 446 .clkdm_name = "l3init_clkdm", 447 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 448 .main_clk = "func_48m_fclk", 449 .mpu_rt_idx = 1, 450 .prcm = { 451 .omap4 = { 452 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, 453 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET, 454 .modulemode = MODULEMODE_SWCTRL, 455 }, 456 }, 457}; 458 459/* 460 * 'vcp' class 461 * 462 */ 463 464static struct omap_hwmod_class dra7xx_vcp_hwmod_class = { 465 .name = "vcp", 466}; 467 468/* vcp1 */ 469static struct omap_hwmod dra7xx_vcp1_hwmod = { 470 .name = "vcp1", 471 .class = &dra7xx_vcp_hwmod_class, 472 .clkdm_name = "l3main1_clkdm", 473 .main_clk = "l3_iclk_div", 474 .prcm = { 475 .omap4 = { 476 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET, 477 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET, 478 }, 479 }, 480}; 481 482/* vcp2 */ 483static struct omap_hwmod dra7xx_vcp2_hwmod = { 484 .name = "vcp2", 485 .class = &dra7xx_vcp_hwmod_class, 486 .clkdm_name = "l3main1_clkdm", 487 .main_clk = "l3_iclk_div", 488 .prcm = { 489 .omap4 = { 490 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET, 491 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET, 492 }, 493 }, 494}; 495 496 497 498/* 499 * Interfaces 500 */ 501 502/* l3_main_1 -> dmm */ 503static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = { 504 .master = &dra7xx_l3_main_1_hwmod, 505 .slave = &dra7xx_dmm_hwmod, 506 .clk = "l3_iclk_div", 507 .user = OCP_USER_SDMA, 508}; 509 510/* l3_main_2 -> l3_instr */ 511static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = { 512 .master = &dra7xx_l3_main_2_hwmod, 513 .slave = &dra7xx_l3_instr_hwmod, 514 .clk = "l3_iclk_div", 515 .user = OCP_USER_MPU | OCP_USER_SDMA, 516}; 517 518/* l4_cfg -> l3_main_1 */ 519static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = { 520 .master = &dra7xx_l4_cfg_hwmod, 521 .slave = &dra7xx_l3_main_1_hwmod, 522 .clk = "l3_iclk_div", 523 .user = OCP_USER_MPU | OCP_USER_SDMA, 524}; 525 526/* mpu -> l3_main_1 */ 527static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = { 528 .master = &dra7xx_mpu_hwmod, 529 .slave = &dra7xx_l3_main_1_hwmod, 530 .clk = "l3_iclk_div", 531 .user = OCP_USER_MPU, 532}; 533 534/* l3_main_1 -> l3_main_2 */ 535static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = { 536 .master = &dra7xx_l3_main_1_hwmod, 537 .slave = &dra7xx_l3_main_2_hwmod, 538 .clk = "l3_iclk_div", 539 .user = OCP_USER_MPU, 540}; 541 542/* l4_cfg -> l3_main_2 */ 543static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = { 544 .master = &dra7xx_l4_cfg_hwmod, 545 .slave = &dra7xx_l3_main_2_hwmod, 546 .clk = "l3_iclk_div", 547 .user = OCP_USER_MPU | OCP_USER_SDMA, 548}; 549 550/* l3_main_1 -> l4_cfg */ 551static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { 552 .master = &dra7xx_l3_main_1_hwmod, 553 .slave = &dra7xx_l4_cfg_hwmod, 554 .clk = "l3_iclk_div", 555 .user = OCP_USER_MPU | OCP_USER_SDMA, 556}; 557 558/* l3_main_1 -> l4_per1 */ 559static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = { 560 .master = &dra7xx_l3_main_1_hwmod, 561 .slave = &dra7xx_l4_per1_hwmod, 562 .clk = "l3_iclk_div", 563 .user = OCP_USER_MPU | OCP_USER_SDMA, 564}; 565 566/* l3_main_1 -> l4_per2 */ 567static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = { 568 .master = &dra7xx_l3_main_1_hwmod, 569 .slave = &dra7xx_l4_per2_hwmod, 570 .clk = "l3_iclk_div", 571 .user = OCP_USER_MPU | OCP_USER_SDMA, 572}; 573 574/* l3_main_1 -> l4_per3 */ 575static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = { 576 .master = &dra7xx_l3_main_1_hwmod, 577 .slave = &dra7xx_l4_per3_hwmod, 578 .clk = "l3_iclk_div", 579 .user = OCP_USER_MPU | OCP_USER_SDMA, 580}; 581 582/* l3_main_1 -> l4_wkup */ 583static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = { 584 .master = &dra7xx_l3_main_1_hwmod, 585 .slave = &dra7xx_l4_wkup_hwmod, 586 .clk = "wkupaon_iclk_mux", 587 .user = OCP_USER_MPU | OCP_USER_SDMA, 588}; 589 590/* l4_per2 -> atl */ 591static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = { 592 .master = &dra7xx_l4_per2_hwmod, 593 .slave = &dra7xx_atl_hwmod, 594 .clk = "l3_iclk_div", 595 .user = OCP_USER_MPU | OCP_USER_SDMA, 596}; 597 598/* l3_main_1 -> bb2d */ 599static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = { 600 .master = &dra7xx_l3_main_1_hwmod, 601 .slave = &dra7xx_bb2d_hwmod, 602 .clk = "l3_iclk_div", 603 .user = OCP_USER_MPU | OCP_USER_SDMA, 604}; 605 606/* l4_wkup -> ctrl_module_wkup */ 607static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { 608 .master = &dra7xx_l4_wkup_hwmod, 609 .slave = &dra7xx_ctrl_module_wkup_hwmod, 610 .clk = "wkupaon_iclk_mux", 611 .user = OCP_USER_MPU | OCP_USER_SDMA, 612}; 613 614/* l3_main_1 -> gpmc */ 615static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { 616 .master = &dra7xx_l3_main_1_hwmod, 617 .slave = &dra7xx_gpmc_hwmod, 618 .clk = "l3_iclk_div", 619 .user = OCP_USER_MPU | OCP_USER_SDMA, 620}; 621 622/* l4_cfg -> mpu */ 623static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { 624 .master = &dra7xx_l4_cfg_hwmod, 625 .slave = &dra7xx_mpu_hwmod, 626 .clk = "l3_iclk_div", 627 .user = OCP_USER_MPU | OCP_USER_SDMA, 628}; 629 630/* l3_main_1 -> pciess1 */ 631static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = { 632 .master = &dra7xx_l3_main_1_hwmod, 633 .slave = &dra7xx_pciess1_hwmod, 634 .clk = "l3_iclk_div", 635 .user = OCP_USER_MPU | OCP_USER_SDMA, 636}; 637 638/* l4_cfg -> pciess1 */ 639static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = { 640 .master = &dra7xx_l4_cfg_hwmod, 641 .slave = &dra7xx_pciess1_hwmod, 642 .clk = "l4_root_clk_div", 643 .user = OCP_USER_MPU | OCP_USER_SDMA, 644}; 645 646/* l3_main_1 -> pciess2 */ 647static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = { 648 .master = &dra7xx_l3_main_1_hwmod, 649 .slave = &dra7xx_pciess2_hwmod, 650 .clk = "l3_iclk_div", 651 .user = OCP_USER_MPU | OCP_USER_SDMA, 652}; 653 654/* l4_cfg -> pciess2 */ 655static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = { 656 .master = &dra7xx_l4_cfg_hwmod, 657 .slave = &dra7xx_pciess2_hwmod, 658 .clk = "l4_root_clk_div", 659 .user = OCP_USER_MPU | OCP_USER_SDMA, 660}; 661 662/* l3_main_1 -> qspi */ 663static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { 664 .master = &dra7xx_l3_main_1_hwmod, 665 .slave = &dra7xx_qspi_hwmod, 666 .clk = "l3_iclk_div", 667 .user = OCP_USER_MPU | OCP_USER_SDMA, 668}; 669 670/* l4_cfg -> sata */ 671static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { 672 .master = &dra7xx_l4_cfg_hwmod, 673 .slave = &dra7xx_sata_hwmod, 674 .clk = "l3_iclk_div", 675 .user = OCP_USER_MPU | OCP_USER_SDMA, 676}; 677 678/* l3_main_1 -> vcp1 */ 679static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = { 680 .master = &dra7xx_l3_main_1_hwmod, 681 .slave = &dra7xx_vcp1_hwmod, 682 .clk = "l3_iclk_div", 683 .user = OCP_USER_MPU | OCP_USER_SDMA, 684}; 685 686/* l4_per2 -> vcp1 */ 687static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = { 688 .master = &dra7xx_l4_per2_hwmod, 689 .slave = &dra7xx_vcp1_hwmod, 690 .clk = "l3_iclk_div", 691 .user = OCP_USER_MPU | OCP_USER_SDMA, 692}; 693 694/* l3_main_1 -> vcp2 */ 695static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = { 696 .master = &dra7xx_l3_main_1_hwmod, 697 .slave = &dra7xx_vcp2_hwmod, 698 .clk = "l3_iclk_div", 699 .user = OCP_USER_MPU | OCP_USER_SDMA, 700}; 701 702/* l4_per2 -> vcp2 */ 703static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = { 704 .master = &dra7xx_l4_per2_hwmod, 705 .slave = &dra7xx_vcp2_hwmod, 706 .clk = "l3_iclk_div", 707 .user = OCP_USER_MPU | OCP_USER_SDMA, 708}; 709 710static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { 711 &dra7xx_l3_main_1__dmm, 712 &dra7xx_l3_main_2__l3_instr, 713 &dra7xx_l4_cfg__l3_main_1, 714 &dra7xx_mpu__l3_main_1, 715 &dra7xx_l3_main_1__l3_main_2, 716 &dra7xx_l4_cfg__l3_main_2, 717 &dra7xx_l3_main_1__l4_cfg, 718 &dra7xx_l3_main_1__l4_per1, 719 &dra7xx_l3_main_1__l4_per2, 720 &dra7xx_l3_main_1__l4_per3, 721 &dra7xx_l3_main_1__l4_wkup, 722 &dra7xx_l4_per2__atl, 723 &dra7xx_l3_main_1__bb2d, 724 &dra7xx_l4_wkup__ctrl_module_wkup, 725 &dra7xx_l3_main_1__gpmc, 726 &dra7xx_l4_cfg__mpu, 727 &dra7xx_l3_main_1__pciess1, 728 &dra7xx_l4_cfg__pciess1, 729 &dra7xx_l3_main_1__pciess2, 730 &dra7xx_l4_cfg__pciess2, 731 &dra7xx_l3_main_1__qspi, 732 &dra7xx_l4_cfg__sata, 733 &dra7xx_l3_main_1__vcp1, 734 &dra7xx_l4_per2__vcp1, 735 &dra7xx_l3_main_1__vcp2, 736 &dra7xx_l4_per2__vcp2, 737 NULL, 738}; 739 740/* SoC variant specific hwmod links */ 741static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { 742 NULL, 743}; 744 745static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = { 746 NULL, 747}; 748 749int __init dra7xx_hwmod_init(void) 750{ 751 int ret; 752 753 omap_hwmod_init(); 754 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); 755 756 if (!ret && soc_is_dra74x()) { 757 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); 758 } else if (!ret && soc_is_dra72x()) { 759 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); 760 if (!ret && !of_machine_is_compatible("ti,dra718")) 761 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); 762 } else if (!ret && soc_is_dra76x()) { 763 if (!ret && soc_is_dra76x_abz()) 764 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); 765 } 766 767 return ret; 768} 769