18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * omap4-sar-layout.h: OMAP4 SAR RAM layout header file 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2011 Texas Instruments, Inc. 68c2ecf20Sopenharmony_ci * Santosh Shilimkar <santosh.shilimkar@ti.com> 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H 98c2ecf20Sopenharmony_ci#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* 128c2ecf20Sopenharmony_ci * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE 138c2ecf20Sopenharmony_ci */ 148c2ecf20Sopenharmony_ci#define SAR_BANK1_OFFSET 0x0000 158c2ecf20Sopenharmony_ci#define SAR_BANK2_OFFSET 0x1000 168c2ecf20Sopenharmony_ci#define SAR_BANK3_OFFSET 0x2000 178c2ecf20Sopenharmony_ci#define SAR_BANK4_OFFSET 0x3000 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci/* Scratch pad memory offsets from SAR_BANK1 */ 208c2ecf20Sopenharmony_ci#define SCU_OFFSET0 0xfe4 218c2ecf20Sopenharmony_ci#define SCU_OFFSET1 0xfe8 228c2ecf20Sopenharmony_ci#define OMAP_TYPE_OFFSET 0xfec 238c2ecf20Sopenharmony_ci#define L2X0_SAVE_OFFSET0 0xff0 248c2ecf20Sopenharmony_ci#define L2X0_SAVE_OFFSET1 0xff4 258c2ecf20Sopenharmony_ci#define L2X0_AUXCTRL_OFFSET 0xff8 268c2ecf20Sopenharmony_ci#define L2X0_PREFETCH_CTRL_OFFSET 0xffc 278c2ecf20Sopenharmony_ci 288c2ecf20Sopenharmony_ci/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */ 298c2ecf20Sopenharmony_ci#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 308c2ecf20Sopenharmony_ci#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08 318c2ecf20Sopenharmony_ci#define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00 328c2ecf20Sopenharmony_ci#define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci#define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500) 358c2ecf20Sopenharmony_ci#define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504) 368c2ecf20Sopenharmony_ci#define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508) 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */ 398c2ecf20Sopenharmony_ci#define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684) 408c2ecf20Sopenharmony_ci#define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694) 418c2ecf20Sopenharmony_ci#define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4) 428c2ecf20Sopenharmony_ci#define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4) 438c2ecf20Sopenharmony_ci#define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4) 448c2ecf20Sopenharmony_ci#define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8) 458c2ecf20Sopenharmony_ci#define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc) 468c2ecf20Sopenharmony_ci#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0) 478c2ecf20Sopenharmony_ci#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ 508c2ecf20Sopenharmony_ci#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) 518c2ecf20Sopenharmony_ci#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) 528c2ecf20Sopenharmony_ci#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) 538c2ecf20Sopenharmony_ci#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) 548c2ecf20Sopenharmony_ci#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) 558c2ecf20Sopenharmony_ci#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) 568c2ecf20Sopenharmony_ci#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) 578c2ecf20Sopenharmony_ci#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) 588c2ecf20Sopenharmony_ci 598c2ecf20Sopenharmony_ci#endif 60