1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/arch/arm/mach-omap2/io.c 4 * 5 * OMAP2 I/O mapping code 6 * 7 * Copyright (C) 2005 Nokia Corporation 8 * Copyright (C) 2007-2009 Texas Instruments 9 * 10 * Author: 11 * Juha Yrjola <juha.yrjola@nokia.com> 12 * Syed Khasim <x0khasim@ti.com> 13 * 14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 15 */ 16#include <linux/module.h> 17#include <linux/kernel.h> 18#include <linux/init.h> 19#include <linux/io.h> 20#include <linux/clk.h> 21 22#include <asm/tlb.h> 23#include <asm/mach/map.h> 24 25#include <linux/omap-dma.h> 26 27#include "omap_hwmod.h" 28#include "soc.h" 29#include "iomap.h" 30#include "voltage.h" 31#include "powerdomain.h" 32#include "clockdomain.h" 33#include "common.h" 34#include "clock.h" 35#include "clock2xxx.h" 36#include "clock3xxx.h" 37#include "sdrc.h" 38#include "control.h" 39#include "serial.h" 40#include "sram.h" 41#include "cm2xxx.h" 42#include "cm3xxx.h" 43#include "cm33xx.h" 44#include "cm44xx.h" 45#include "prm.h" 46#include "cm.h" 47#include "prcm_mpu44xx.h" 48#include "prminst44xx.h" 49#include "prm2xxx.h" 50#include "prm3xxx.h" 51#include "prm33xx.h" 52#include "prm44xx.h" 53#include "opp2xxx.h" 54#include "omap-secure.h" 55 56/* 57 * omap_clk_soc_init: points to a function that does the SoC-specific 58 * clock initializations 59 */ 60static int (*omap_clk_soc_init)(void); 61 62/* 63 * The machine specific code may provide the extra mapping besides the 64 * default mapping provided here. 65 */ 66 67#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) 68static struct map_desc omap24xx_io_desc[] __initdata = { 69 { 70 .virtual = L3_24XX_VIRT, 71 .pfn = __phys_to_pfn(L3_24XX_PHYS), 72 .length = L3_24XX_SIZE, 73 .type = MT_DEVICE 74 }, 75 { 76 .virtual = L4_24XX_VIRT, 77 .pfn = __phys_to_pfn(L4_24XX_PHYS), 78 .length = L4_24XX_SIZE, 79 .type = MT_DEVICE 80 }, 81}; 82 83#ifdef CONFIG_SOC_OMAP2420 84static struct map_desc omap242x_io_desc[] __initdata = { 85 { 86 .virtual = DSP_MEM_2420_VIRT, 87 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 88 .length = DSP_MEM_2420_SIZE, 89 .type = MT_DEVICE 90 }, 91 { 92 .virtual = DSP_IPI_2420_VIRT, 93 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 94 .length = DSP_IPI_2420_SIZE, 95 .type = MT_DEVICE 96 }, 97 { 98 .virtual = DSP_MMU_2420_VIRT, 99 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 100 .length = DSP_MMU_2420_SIZE, 101 .type = MT_DEVICE 102 }, 103}; 104 105#endif 106 107#ifdef CONFIG_SOC_OMAP2430 108static struct map_desc omap243x_io_desc[] __initdata = { 109 { 110 .virtual = L4_WK_243X_VIRT, 111 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 112 .length = L4_WK_243X_SIZE, 113 .type = MT_DEVICE 114 }, 115 { 116 .virtual = OMAP243X_GPMC_VIRT, 117 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 118 .length = OMAP243X_GPMC_SIZE, 119 .type = MT_DEVICE 120 }, 121 { 122 .virtual = OMAP243X_SDRC_VIRT, 123 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 124 .length = OMAP243X_SDRC_SIZE, 125 .type = MT_DEVICE 126 }, 127 { 128 .virtual = OMAP243X_SMS_VIRT, 129 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 130 .length = OMAP243X_SMS_SIZE, 131 .type = MT_DEVICE 132 }, 133}; 134#endif 135#endif 136 137#ifdef CONFIG_ARCH_OMAP3 138static struct map_desc omap34xx_io_desc[] __initdata = { 139 { 140 .virtual = L3_34XX_VIRT, 141 .pfn = __phys_to_pfn(L3_34XX_PHYS), 142 .length = L3_34XX_SIZE, 143 .type = MT_DEVICE 144 }, 145 { 146 .virtual = L4_34XX_VIRT, 147 .pfn = __phys_to_pfn(L4_34XX_PHYS), 148 .length = L4_34XX_SIZE, 149 .type = MT_DEVICE 150 }, 151 { 152 .virtual = OMAP34XX_GPMC_VIRT, 153 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 154 .length = OMAP34XX_GPMC_SIZE, 155 .type = MT_DEVICE 156 }, 157 { 158 .virtual = OMAP343X_SMS_VIRT, 159 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 160 .length = OMAP343X_SMS_SIZE, 161 .type = MT_DEVICE 162 }, 163 { 164 .virtual = OMAP343X_SDRC_VIRT, 165 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 166 .length = OMAP343X_SDRC_SIZE, 167 .type = MT_DEVICE 168 }, 169 { 170 .virtual = L4_PER_34XX_VIRT, 171 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 172 .length = L4_PER_34XX_SIZE, 173 .type = MT_DEVICE 174 }, 175 { 176 .virtual = L4_EMU_34XX_VIRT, 177 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 178 .length = L4_EMU_34XX_SIZE, 179 .type = MT_DEVICE 180 }, 181}; 182#endif 183 184#ifdef CONFIG_SOC_TI81XX 185static struct map_desc omapti81xx_io_desc[] __initdata = { 186 { 187 .virtual = L4_34XX_VIRT, 188 .pfn = __phys_to_pfn(L4_34XX_PHYS), 189 .length = L4_34XX_SIZE, 190 .type = MT_DEVICE 191 } 192}; 193#endif 194 195#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 196static struct map_desc omapam33xx_io_desc[] __initdata = { 197 { 198 .virtual = L4_34XX_VIRT, 199 .pfn = __phys_to_pfn(L4_34XX_PHYS), 200 .length = L4_34XX_SIZE, 201 .type = MT_DEVICE 202 }, 203 { 204 .virtual = L4_WK_AM33XX_VIRT, 205 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), 206 .length = L4_WK_AM33XX_SIZE, 207 .type = MT_DEVICE 208 } 209}; 210#endif 211 212#ifdef CONFIG_ARCH_OMAP4 213static struct map_desc omap44xx_io_desc[] __initdata = { 214 { 215 .virtual = L3_44XX_VIRT, 216 .pfn = __phys_to_pfn(L3_44XX_PHYS), 217 .length = L3_44XX_SIZE, 218 .type = MT_DEVICE, 219 }, 220 { 221 .virtual = L4_44XX_VIRT, 222 .pfn = __phys_to_pfn(L4_44XX_PHYS), 223 .length = L4_44XX_SIZE, 224 .type = MT_DEVICE, 225 }, 226 { 227 .virtual = L4_PER_44XX_VIRT, 228 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 229 .length = L4_PER_44XX_SIZE, 230 .type = MT_DEVICE, 231 }, 232}; 233#endif 234 235#ifdef CONFIG_SOC_OMAP5 236static struct map_desc omap54xx_io_desc[] __initdata = { 237 { 238 .virtual = L3_54XX_VIRT, 239 .pfn = __phys_to_pfn(L3_54XX_PHYS), 240 .length = L3_54XX_SIZE, 241 .type = MT_DEVICE, 242 }, 243 { 244 .virtual = L4_54XX_VIRT, 245 .pfn = __phys_to_pfn(L4_54XX_PHYS), 246 .length = L4_54XX_SIZE, 247 .type = MT_DEVICE, 248 }, 249 { 250 .virtual = L4_WK_54XX_VIRT, 251 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), 252 .length = L4_WK_54XX_SIZE, 253 .type = MT_DEVICE, 254 }, 255 { 256 .virtual = L4_PER_54XX_VIRT, 257 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), 258 .length = L4_PER_54XX_SIZE, 259 .type = MT_DEVICE, 260 }, 261}; 262#endif 263 264#ifdef CONFIG_SOC_DRA7XX 265static struct map_desc dra7xx_io_desc[] __initdata = { 266 { 267 .virtual = L4_CFG_MPU_DRA7XX_VIRT, 268 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS), 269 .length = L4_CFG_MPU_DRA7XX_SIZE, 270 .type = MT_DEVICE, 271 }, 272 { 273 .virtual = L3_MAIN_SN_DRA7XX_VIRT, 274 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS), 275 .length = L3_MAIN_SN_DRA7XX_SIZE, 276 .type = MT_DEVICE, 277 }, 278 { 279 .virtual = L4_PER1_DRA7XX_VIRT, 280 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS), 281 .length = L4_PER1_DRA7XX_SIZE, 282 .type = MT_DEVICE, 283 }, 284 { 285 .virtual = L4_PER2_DRA7XX_VIRT, 286 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS), 287 .length = L4_PER2_DRA7XX_SIZE, 288 .type = MT_DEVICE, 289 }, 290 { 291 .virtual = L4_PER3_DRA7XX_VIRT, 292 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS), 293 .length = L4_PER3_DRA7XX_SIZE, 294 .type = MT_DEVICE, 295 }, 296 { 297 .virtual = L4_CFG_DRA7XX_VIRT, 298 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS), 299 .length = L4_CFG_DRA7XX_SIZE, 300 .type = MT_DEVICE, 301 }, 302 { 303 .virtual = L4_WKUP_DRA7XX_VIRT, 304 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS), 305 .length = L4_WKUP_DRA7XX_SIZE, 306 .type = MT_DEVICE, 307 }, 308}; 309#endif 310 311#ifdef CONFIG_SOC_OMAP2420 312void __init omap242x_map_io(void) 313{ 314 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 315 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 316} 317#endif 318 319#ifdef CONFIG_SOC_OMAP2430 320void __init omap243x_map_io(void) 321{ 322 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 323 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 324} 325#endif 326 327#ifdef CONFIG_ARCH_OMAP3 328void __init omap3_map_io(void) 329{ 330 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 331} 332#endif 333 334#ifdef CONFIG_SOC_TI81XX 335void __init ti81xx_map_io(void) 336{ 337 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); 338} 339#endif 340 341#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 342void __init am33xx_map_io(void) 343{ 344 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 345} 346#endif 347 348#ifdef CONFIG_ARCH_OMAP4 349void __init omap4_map_io(void) 350{ 351 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 352 omap_barriers_init(); 353} 354#endif 355 356#ifdef CONFIG_SOC_OMAP5 357void __init omap5_map_io(void) 358{ 359 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 360 omap_barriers_init(); 361} 362#endif 363 364#ifdef CONFIG_SOC_DRA7XX 365void __init dra7xx_map_io(void) 366{ 367 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc)); 368 omap_barriers_init(); 369} 370#endif 371/* 372 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 373 * 374 * Sets the CORE DPLL3 M2 divider to the same value that it's at 375 * currently. This has the effect of setting the SDRC SDRAM AC timing 376 * registers to the values currently defined by the kernel. Currently 377 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 378 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 379 * or passes along the return value of clk_set_rate(). 380 */ 381static int __init _omap2_init_reprogram_sdrc(void) 382{ 383 struct clk *dpll3_m2_ck; 384 int v = -EINVAL; 385 long rate; 386 387 if (!cpu_is_omap34xx()) 388 return 0; 389 390 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 391 if (IS_ERR(dpll3_m2_ck)) 392 return -EINVAL; 393 394 rate = clk_get_rate(dpll3_m2_ck); 395 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 396 v = clk_set_rate(dpll3_m2_ck, rate); 397 if (v) 398 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 399 400 clk_put(dpll3_m2_ck); 401 402 return v; 403} 404 405static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) 406{ 407 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 408} 409 410static void __init __maybe_unused omap_hwmod_init_postsetup(void) 411{ 412 u8 postsetup_state = _HWMOD_STATE_DEFAULT; 413 414 /* Set the default postsetup state for all hwmods */ 415 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 416} 417 418#ifdef CONFIG_SOC_OMAP2420 419void __init omap2420_init_early(void) 420{ 421 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); 422 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), 423 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); 424 omap2_control_base_init(); 425 omap2xxx_check_revision(); 426 omap2_prcm_base_init(); 427 omap2xxx_voltagedomains_init(); 428 omap242x_powerdomains_init(); 429 omap242x_clockdomains_init(); 430 omap2420_hwmod_init(); 431 omap_hwmod_init_postsetup(); 432 omap_clk_soc_init = omap2420_dt_clk_init; 433 rate_table = omap2420_rate_table; 434} 435 436void __init omap2420_init_late(void) 437{ 438 omap_pm_soc_init = omap2_pm_init; 439} 440#endif 441 442#ifdef CONFIG_SOC_OMAP2430 443void __init omap2430_init_early(void) 444{ 445 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); 446 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), 447 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); 448 omap2_control_base_init(); 449 omap2xxx_check_revision(); 450 omap2_prcm_base_init(); 451 omap2xxx_voltagedomains_init(); 452 omap243x_powerdomains_init(); 453 omap243x_clockdomains_init(); 454 omap2430_hwmod_init(); 455 omap_hwmod_init_postsetup(); 456 omap_clk_soc_init = omap2430_dt_clk_init; 457 rate_table = omap2430_rate_table; 458} 459 460void __init omap2430_init_late(void) 461{ 462 omap_pm_soc_init = omap2_pm_init; 463} 464#endif 465 466/* 467 * Currently only board-omap3beagle.c should call this because of the 468 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. 469 */ 470#ifdef CONFIG_ARCH_OMAP3 471void __init omap3_init_early(void) 472{ 473 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 474 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 475 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 476 omap2_control_base_init(); 477 omap3xxx_check_revision(); 478 omap3xxx_check_features(); 479 omap2_prcm_base_init(); 480 omap3xxx_voltagedomains_init(); 481 omap3xxx_powerdomains_init(); 482 omap3xxx_clockdomains_init(); 483 omap3xxx_hwmod_init(); 484 omap_hwmod_init_postsetup(); 485 omap_secure_init(); 486} 487 488void __init omap3430_init_early(void) 489{ 490 omap3_init_early(); 491 omap_clk_soc_init = omap3430_dt_clk_init; 492} 493 494void __init omap35xx_init_early(void) 495{ 496 omap3_init_early(); 497 omap_clk_soc_init = omap3430_dt_clk_init; 498} 499 500void __init omap3630_init_early(void) 501{ 502 omap3_init_early(); 503 omap_clk_soc_init = omap3630_dt_clk_init; 504} 505 506void __init am35xx_init_early(void) 507{ 508 omap3_init_early(); 509 omap_clk_soc_init = am35xx_dt_clk_init; 510} 511 512void __init omap3_init_late(void) 513{ 514 omap_pm_soc_init = omap3_pm_init; 515} 516 517void __init ti81xx_init_late(void) 518{ 519 omap_pm_soc_init = omap_pm_nop_init; 520} 521#endif 522 523#ifdef CONFIG_SOC_TI81XX 524void __init ti814x_init_early(void) 525{ 526 omap2_set_globals_tap(TI814X_CLASS, 527 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 528 omap2_control_base_init(); 529 omap3xxx_check_revision(); 530 ti81xx_check_features(); 531 omap2_prcm_base_init(); 532 omap3xxx_voltagedomains_init(); 533 omap3xxx_powerdomains_init(); 534 ti814x_clockdomains_init(); 535 dm814x_hwmod_init(); 536 omap_hwmod_init_postsetup(); 537 omap_clk_soc_init = dm814x_dt_clk_init; 538 omap_secure_init(); 539} 540 541void __init ti816x_init_early(void) 542{ 543 omap2_set_globals_tap(TI816X_CLASS, 544 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 545 omap2_control_base_init(); 546 omap3xxx_check_revision(); 547 ti81xx_check_features(); 548 omap2_prcm_base_init(); 549 omap3xxx_voltagedomains_init(); 550 omap3xxx_powerdomains_init(); 551 ti816x_clockdomains_init(); 552 dm816x_hwmod_init(); 553 omap_hwmod_init_postsetup(); 554 omap_clk_soc_init = dm816x_dt_clk_init; 555 omap_secure_init(); 556} 557#endif 558 559#ifdef CONFIG_SOC_AM33XX 560void __init am33xx_init_early(void) 561{ 562 omap2_set_globals_tap(AM335X_CLASS, 563 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 564 omap2_control_base_init(); 565 omap3xxx_check_revision(); 566 am33xx_check_features(); 567 omap2_prcm_base_init(); 568 am33xx_powerdomains_init(); 569 am33xx_clockdomains_init(); 570 am33xx_hwmod_init(); 571 omap_hwmod_init_postsetup(); 572 omap_clk_soc_init = am33xx_dt_clk_init; 573 omap_secure_init(); 574} 575 576void __init am33xx_init_late(void) 577{ 578 omap_pm_soc_init = amx3_common_pm_init; 579} 580#endif 581 582#ifdef CONFIG_SOC_AM43XX 583void __init am43xx_init_early(void) 584{ 585 omap2_set_globals_tap(AM335X_CLASS, 586 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 587 omap2_control_base_init(); 588 omap3xxx_check_revision(); 589 am33xx_check_features(); 590 omap2_prcm_base_init(); 591 am43xx_powerdomains_init(); 592 am43xx_clockdomains_init(); 593 am43xx_hwmod_init(); 594 omap_hwmod_init_postsetup(); 595 omap_l2_cache_init(); 596 omap_clk_soc_init = am43xx_dt_clk_init; 597 omap_secure_init(); 598} 599 600void __init am43xx_init_late(void) 601{ 602 omap_pm_soc_init = amx3_common_pm_init; 603} 604#endif 605 606#ifdef CONFIG_ARCH_OMAP4 607void __init omap4430_init_early(void) 608{ 609 omap2_set_globals_tap(OMAP443X_CLASS, 610 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); 611 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); 612 omap2_control_base_init(); 613 omap4xxx_check_revision(); 614 omap4xxx_check_features(); 615 omap2_prcm_base_init(); 616 omap4_sar_ram_init(); 617 omap4_mpuss_early_init(); 618 omap4_pm_init_early(); 619 omap44xx_voltagedomains_init(); 620 omap44xx_powerdomains_init(); 621 omap44xx_clockdomains_init(); 622 omap44xx_hwmod_init(); 623 omap_hwmod_init_postsetup(); 624 omap_l2_cache_init(); 625 omap_clk_soc_init = omap4xxx_dt_clk_init; 626 omap_secure_init(); 627} 628 629void __init omap4430_init_late(void) 630{ 631 omap_pm_soc_init = omap4_pm_init; 632} 633#endif 634 635#ifdef CONFIG_SOC_OMAP5 636void __init omap5_init_early(void) 637{ 638 omap2_set_globals_tap(OMAP54XX_CLASS, 639 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 640 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 641 omap2_control_base_init(); 642 omap2_prcm_base_init(); 643 omap5xxx_check_revision(); 644 omap4_sar_ram_init(); 645 omap4_mpuss_early_init(); 646 omap4_pm_init_early(); 647 omap54xx_voltagedomains_init(); 648 omap54xx_powerdomains_init(); 649 omap54xx_clockdomains_init(); 650 omap54xx_hwmod_init(); 651 omap_hwmod_init_postsetup(); 652 omap_clk_soc_init = omap5xxx_dt_clk_init; 653 omap_secure_init(); 654} 655 656void __init omap5_init_late(void) 657{ 658 omap_pm_soc_init = omap4_pm_init; 659} 660#endif 661 662#ifdef CONFIG_SOC_DRA7XX 663void __init dra7xx_init_early(void) 664{ 665 omap2_set_globals_tap(DRA7XX_CLASS, 666 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); 667 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 668 omap2_control_base_init(); 669 omap4_pm_init_early(); 670 omap2_prcm_base_init(); 671 dra7xxx_check_revision(); 672 dra7xx_powerdomains_init(); 673 dra7xx_clockdomains_init(); 674 dra7xx_hwmod_init(); 675 omap_hwmod_init_postsetup(); 676 omap_clk_soc_init = dra7xx_dt_clk_init; 677 omap_secure_init(); 678} 679 680void __init dra7xx_init_late(void) 681{ 682 omap_pm_soc_init = omap4_pm_init; 683} 684#endif 685 686 687void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 688 struct omap_sdrc_params *sdrc_cs1) 689{ 690 omap_sram_init(); 691 692 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 693 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 694 _omap2_init_reprogram_sdrc(); 695 } 696} 697 698int __init omap_clk_init(void) 699{ 700 int ret = 0; 701 702 if (!omap_clk_soc_init) 703 return 0; 704 705 ti_clk_init_features(); 706 707 omap2_clk_setup_ll_ops(); 708 709 ret = omap_control_init(); 710 if (ret) 711 return ret; 712 713 ret = omap_prcm_init(); 714 if (ret) 715 return ret; 716 717 of_clk_init(NULL); 718 719 ti_dt_clk_init_retry_clks(); 720 721 ti_dt_clockdomains_setup(); 722 723 ret = omap_clk_soc_init(); 724 725 return ret; 726} 727