1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * OMAP44xx Clock Management register bits
4 *
5 * Copyright (C) 2009-2012 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
7 *
8 * Paul Walmsley (paul@pwsan.com)
9 * Rajendra Nayak (rnayak@ti.com)
10 * Benoit Cousson (b-cousson@ti.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
20#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
21
22#define OMAP4430_ABE_STATDEP_SHIFT				3
23#define OMAP4430_AUTO_DPLL_MODE_MASK				(0x7 << 0)
24#define OMAP4430_CLKSEL_SHIFT					24
25#define OMAP4430_CLKSEL_WIDTH					0x1
26#define OMAP4430_CLKSEL_MASK					(1 << 24)
27#define OMAP4430_CLKSEL_0_0_SHIFT				0
28#define OMAP4430_CLKSEL_0_0_WIDTH				0x1
29#define OMAP4430_CLKSEL_0_1_SHIFT				0
30#define OMAP4430_CLKSEL_0_1_WIDTH				0x2
31#define OMAP4430_CLKSEL_24_25_SHIFT				24
32#define OMAP4430_CLKSEL_24_25_WIDTH				0x2
33#define OMAP4430_CLKSEL_60M_SHIFT				24
34#define OMAP4430_CLKSEL_60M_WIDTH				0x1
35#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT				24
36#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH				0x1
37#define OMAP4430_CLKSEL_CORE_SHIFT				0
38#define OMAP4430_CLKSEL_CORE_WIDTH				0x1
39#define OMAP4430_CLKSEL_DIV_SHIFT				24
40#define OMAP4430_CLKSEL_DIV_WIDTH				0x1
41#define OMAP4430_CLKSEL_FCLK_SHIFT				24
42#define OMAP4430_CLKSEL_FCLK_WIDTH				0x2
43#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT			25
44#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH			0x1
45#define OMAP4430_CLKSEL_L3_SHIFT				4
46#define OMAP4430_CLKSEL_L3_WIDTH				0x1
47#define OMAP4430_CLKSEL_L4_SHIFT				8
48#define OMAP4430_CLKSEL_L4_WIDTH				0x1
49#define OMAP4430_CLKSEL_OPP_SHIFT				0
50#define OMAP4430_CLKSEL_OPP_WIDTH				0x2
51#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT			27
52#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH			0x3
53#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK			(0x7 << 24)
54#define OMAP4430_CLKSEL_SGX_FCLK_MASK				(1 << 24)
55#define OMAP4430_CLKSEL_SOURCE_MASK				(0x3 << 24)
56#define OMAP4430_CLKSEL_SOURCE_24_24_MASK			(1 << 24)
57#define OMAP4430_CLKSEL_UTMI_P1_SHIFT				24
58#define OMAP4430_CLKSEL_UTMI_P1_WIDTH				0x1
59#define OMAP4430_CLKSEL_UTMI_P2_SHIFT				25
60#define OMAP4430_CLKSEL_UTMI_P2_WIDTH				0x1
61#define OMAP4430_CLKTRCTRL_SHIFT				0
62#define OMAP4430_CLKTRCTRL_MASK					(0x3 << 0)
63#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT				23
64#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH				0x1
65#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK			(0x1f << 0)
66#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT			8
67#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK			(1 << 10)
68#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT				0
69#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH				0x5
70#define OMAP4430_DPLL_CLKOUT_DIV_MASK				(0x1f << 0)
71#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK			(0x7f << 0)
72#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK			(1 << 8)
73#define OMAP4430_DPLL_DIV_MASK					(0x7f << 0)
74#define OMAP4430_DPLL_DIV_0_7_MASK				(0xff << 0)
75#define OMAP4430_DPLL_EN_MASK					(0x7 << 0)
76#define OMAP4430_DPLL_LPMODE_EN_MASK				(1 << 10)
77#define OMAP4430_DPLL_MULT_MASK					(0x7ff << 8)
78#define OMAP4430_DPLL_MULT_USB_MASK				(0xfff << 8)
79#define OMAP4430_DPLL_REGM4XEN_MASK				(1 << 11)
80#define OMAP4430_DPLL_SD_DIV_MASK				(0xff << 24)
81#define OMAP4430_DSS_STATDEP_SHIFT				8
82#define OMAP4430_DUCATI_STATDEP_SHIFT				0
83#define OMAP4430_GFX_STATDEP_SHIFT				10
84#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK			(0x1f << 0)
85#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK			(0x1f << 0)
86#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK			(0x1f << 0)
87#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK			(0x1f << 0)
88#define OMAP4430_IDLEST_SHIFT					16
89#define OMAP4430_IDLEST_MASK					(0x3 << 16)
90#define OMAP4430_IVAHD_STATDEP_SHIFT				2
91#define OMAP4430_L3INIT_STATDEP_SHIFT				7
92#define OMAP4430_L3_1_STATDEP_SHIFT				5
93#define OMAP4430_L3_2_STATDEP_SHIFT				6
94#define OMAP4430_L4CFG_STATDEP_SHIFT				12
95#define OMAP4430_L4PER_STATDEP_SHIFT				13
96#define OMAP4430_L4SEC_STATDEP_SHIFT				14
97#define OMAP4430_L4WKUP_STATDEP_SHIFT				15
98#define OMAP4430_MEMIF_STATDEP_SHIFT				4
99#define OMAP4430_MODULEMODE_SHIFT				0
100#define OMAP4430_MODULEMODE_MASK				(0x3 << 0)
101#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT			9
102#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT			8
103#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT				8
104#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT			8
105#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT				8
106#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT				8
107#define OMAP4430_OPTFCLKEN_FCLK_SHIFT				8
108#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT				8
109#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT				9
110#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT				10
111#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT			15
112#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT		13
113#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT		14
114#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT			11
115#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT			12
116#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT			8
117#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT		9
118#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT			8
119#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT			10
120#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT		11
121#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT			10
122#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT			8
123#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT				11
124#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT			8
125#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT			9
126#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT			10
127#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT			8
128#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT			9
129#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT			10
130#define OMAP4430_OPTFCLKEN_XCLK_SHIFT				8
131#define OMAP4430_PAD_CLKS_GATE_SHIFT				8
132#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT				20
133#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH				0x2
134#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT			22
135#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH			0x2
136#define OMAP4430_SCALE_FCLK_SHIFT				0
137#define OMAP4430_SCALE_FCLK_WIDTH				0x1
138#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT				10
139#define OMAP4430_ST_DPLL_CLK_MASK				(1 << 0)
140#define OMAP4430_SYS_CLKSEL_SHIFT				0
141#define OMAP4430_SYS_CLKSEL_WIDTH				0x3
142#define OMAP4430_TESLA_STATDEP_SHIFT				1
143#endif
144