1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *  linux/arch/arm/mach-omap2/clock.c
4 *
5 *  Copyright (C) 2005-2008 Texas Instruments, Inc.
6 *  Copyright (C) 2004-2010 Nokia Corporation
7 *
8 *  Contacts:
9 *  Richard Woodruff <r-woodruff2@ti.com>
10 *  Paul Walmsley
11 */
12#undef DEBUG
13
14#include <linux/kernel.h>
15#include <linux/export.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/clk-provider.h>
22#include <linux/io.h>
23#include <linux/bitops.h>
24#include <linux/of_address.h>
25#include <asm/cpu.h>
26
27#include <trace/events/power.h>
28
29#include "soc.h"
30#include "clockdomain.h"
31#include "clock.h"
32#include "cm.h"
33#include "cm2xxx.h"
34#include "cm3xxx.h"
35#include "cm-regbits-24xx.h"
36#include "cm-regbits-34xx.h"
37#include "common.h"
38
39u16 cpu_mask;
40
41/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
42#define OMAP3430_DPLL_FINT_BAND1_MIN	750000
43#define OMAP3430_DPLL_FINT_BAND1_MAX	2100000
44#define OMAP3430_DPLL_FINT_BAND2_MIN	7500000
45#define OMAP3430_DPLL_FINT_BAND2_MAX	21000000
46
47/*
48 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
49 * From device data manual section 4.3 "DPLL and DLL Specifications".
50 */
51#define OMAP3PLUS_DPLL_FINT_MIN		32000
52#define OMAP3PLUS_DPLL_FINT_MAX		52000000
53
54struct ti_clk_ll_ops omap_clk_ll_ops = {
55	.clkdm_clk_enable = clkdm_clk_enable,
56	.clkdm_clk_disable = clkdm_clk_disable,
57	.clkdm_lookup = clkdm_lookup,
58	.cm_wait_module_ready = omap_cm_wait_module_ready,
59	.cm_split_idlest_reg = cm_split_idlest_reg,
60};
61
62/**
63 * omap2_clk_setup_ll_ops - setup clock driver low-level ops
64 *
65 * Sets up clock driver low-level platform ops. These are needed
66 * for register accesses and various other misc platform operations.
67 * Returns 0 on success, -EBUSY if low level ops have been registered
68 * already.
69 */
70int __init omap2_clk_setup_ll_ops(void)
71{
72	return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
73}
74
75/*
76 * OMAP2+ specific clock functions
77 */
78
79/**
80 * ti_clk_init_features - init clock features struct for the SoC
81 *
82 * Initializes the clock features struct based on the SoC type.
83 */
84void __init ti_clk_init_features(void)
85{
86	struct ti_clk_features features = { 0 };
87	/* Fint setup for DPLLs */
88	if (cpu_is_omap3430()) {
89		features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
90		features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
91		features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
92		features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
93	} else {
94		features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
95		features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
96	}
97
98	/* Bypass value setup for DPLLs */
99	if (cpu_is_omap24xx()) {
100		features.dpll_bypass_vals |=
101			(1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
102			(1 << OMAP2XXX_EN_DPLL_FRBYPASS);
103	} else if (cpu_is_omap34xx()) {
104		features.dpll_bypass_vals |=
105			(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
106			(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
107	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
108		   soc_is_omap54xx() || soc_is_dra7xx()) {
109		features.dpll_bypass_vals |=
110			(1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
111			(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
112			(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
113	}
114
115	/* Jitter correction only available on OMAP343X */
116	if (cpu_is_omap343x())
117		features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
118
119	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
120		features.flags |= TI_CLK_DEVICE_TYPE_GP;
121
122	/* Idlest value for interface clocks.
123	 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
124	 * 34xx reverses this, just to keep us on our toes
125	 * AM35xx uses both, depending on the module.
126	 */
127	if (cpu_is_omap24xx())
128		features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
129	else if (cpu_is_omap34xx())
130		features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
131
132	/* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
133	if (omap_rev() == OMAP3430_REV_ES1_0)
134		features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
135
136	/* Errata I810 for omap5 / dra7 */
137	if (soc_is_omap54xx() || soc_is_dra7xx())
138		features.flags |= TI_CLK_ERRATA_I810;
139
140	ti_clk_setup_features(&features);
141}
142