18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * Copyright (C) 2014 Marvell 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 58c2ecf20Sopenharmony_ci * Gregory Clement <gregory.clement@free-electrons.com> 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * This file is licensed under the terms of the GNU General Public 88c2ecf20Sopenharmony_ci * License version 2. This program is licensed "as is" without any 98c2ecf20Sopenharmony_ci * warranty of any kind, whether express or implied. 108c2ecf20Sopenharmony_ci */ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <linux/linkage.h> 138c2ecf20Sopenharmony_ci#include <asm/assembler.h> 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ciENTRY(armada_38x_scu_power_up) 178c2ecf20Sopenharmony_ci mrc p15, 4, r1, c15, c0 @ get SCU base address 188c2ecf20Sopenharmony_ci orr r1, r1, #0x8 @ SCU CPU Power Status Register 198c2ecf20Sopenharmony_ci mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID 208c2ecf20Sopenharmony_ci and r0, r0, #15 218c2ecf20Sopenharmony_ci add r1, r1, r0 228c2ecf20Sopenharmony_ci mov r0, #0x0 238c2ecf20Sopenharmony_ci strb r0, [r1] @ switch SCU power state to Normal mode 248c2ecf20Sopenharmony_ci ret lr 258c2ecf20Sopenharmony_ciENDPROC(armada_38x_scu_power_up) 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci/* 288c2ecf20Sopenharmony_ci * This is the entry point through which CPUs exiting cpuidle deep 298c2ecf20Sopenharmony_ci * idle state are going. 308c2ecf20Sopenharmony_ci */ 318c2ecf20Sopenharmony_ciENTRY(armada_370_xp_cpu_resume) 328c2ecf20Sopenharmony_ciARM_BE8(setend be ) @ go BE8 if entered LE 338c2ecf20Sopenharmony_ci /* 348c2ecf20Sopenharmony_ci * Disable the MMU that might have been enabled in BootROM if 358c2ecf20Sopenharmony_ci * this code is used in the resume path of a suspend/resume 368c2ecf20Sopenharmony_ci * cycle. 378c2ecf20Sopenharmony_ci */ 388c2ecf20Sopenharmony_ci mrc p15, 0, r1, c1, c0, 0 398c2ecf20Sopenharmony_ci bic r1, #1 408c2ecf20Sopenharmony_ci mcr p15, 0, r1, c1, c0, 0 418c2ecf20Sopenharmony_ci bl ll_add_cpu_to_smp_group 428c2ecf20Sopenharmony_ci bl ll_enable_coherency 438c2ecf20Sopenharmony_ci b cpu_resume 448c2ecf20Sopenharmony_ciENDPROC(armada_370_xp_cpu_resume) 458c2ecf20Sopenharmony_ci 468c2ecf20Sopenharmony_ciENTRY(armada_38x_cpu_resume) 478c2ecf20Sopenharmony_ci /* do we need it for Armada 38x*/ 488c2ecf20Sopenharmony_ciARM_BE8(setend be ) @ go BE8 if entered LE 498c2ecf20Sopenharmony_ci bl v7_invalidate_l1 508c2ecf20Sopenharmony_ci bl armada_38x_scu_power_up 518c2ecf20Sopenharmony_ci b cpu_resume 528c2ecf20Sopenharmony_ciENDPROC(armada_38x_cpu_resume) 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci.global mvebu_boot_wa_start 558c2ecf20Sopenharmony_ci.global mvebu_boot_wa_end 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci/* The following code will be executed from SRAM */ 588c2ecf20Sopenharmony_ciENTRY(mvebu_boot_wa_start) 598c2ecf20Sopenharmony_ciARM_BE8(setend be) 608c2ecf20Sopenharmony_ci adr r0, 1f 618c2ecf20Sopenharmony_ci ldr r0, [r0] @ load the address of the 628c2ecf20Sopenharmony_ci @ resume register 638c2ecf20Sopenharmony_ci ldr r0, [r0] @ load the value in the 648c2ecf20Sopenharmony_ci @ resume register 658c2ecf20Sopenharmony_ciARM_BE8(rev r0, r0) @ the value is stored LE 668c2ecf20Sopenharmony_ci mov pc, r0 @ jump to this value 678c2ecf20Sopenharmony_ci/* 688c2ecf20Sopenharmony_ci * the last word of this piece of code will be filled by the physical 698c2ecf20Sopenharmony_ci * address of the boot address register just after being copied in SRAM 708c2ecf20Sopenharmony_ci */ 718c2ecf20Sopenharmony_ci1: 728c2ecf20Sopenharmony_ci .long . 738c2ecf20Sopenharmony_cimvebu_boot_wa_end: 748c2ecf20Sopenharmony_ciENDPROC(mvebu_boot_wa_end) 75