18c2ecf20Sopenharmony_ci/*
28c2ecf20Sopenharmony_ci * Board-level suspend/resume support.
38c2ecf20Sopenharmony_ci *
48c2ecf20Sopenharmony_ci * Copyright (C) 2014-2015 Marvell
58c2ecf20Sopenharmony_ci *
68c2ecf20Sopenharmony_ci * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
78c2ecf20Sopenharmony_ci *
88c2ecf20Sopenharmony_ci * This file is licensed under the terms of the GNU General Public
98c2ecf20Sopenharmony_ci * License version 2.  This program is licensed "as is" without any
108c2ecf20Sopenharmony_ci * warranty of any kind, whether express or implied.
118c2ecf20Sopenharmony_ci */
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ci#include <linux/delay.h>
148c2ecf20Sopenharmony_ci#include <linux/gpio.h>
158c2ecf20Sopenharmony_ci#include <linux/init.h>
168c2ecf20Sopenharmony_ci#include <linux/io.h>
178c2ecf20Sopenharmony_ci#include <linux/of.h>
188c2ecf20Sopenharmony_ci#include <linux/of_address.h>
198c2ecf20Sopenharmony_ci#include <linux/of_gpio.h>
208c2ecf20Sopenharmony_ci#include <linux/slab.h>
218c2ecf20Sopenharmony_ci#include "common.h"
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci#define ARMADA_PIC_NR_GPIOS 3
248c2ecf20Sopenharmony_ci
258c2ecf20Sopenharmony_cistatic void __iomem *gpio_ctrl;
268c2ecf20Sopenharmony_cistatic int pic_gpios[ARMADA_PIC_NR_GPIOS];
278c2ecf20Sopenharmony_cistatic int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_cistatic void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)
308c2ecf20Sopenharmony_ci{
318c2ecf20Sopenharmony_ci	u32 reg, ackcmd;
328c2ecf20Sopenharmony_ci	int i;
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_ci	/* Put 001 as value on the GPIOs */
358c2ecf20Sopenharmony_ci	reg = readl(gpio_ctrl);
368c2ecf20Sopenharmony_ci	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
378c2ecf20Sopenharmony_ci		reg &= ~BIT(pic_raw_gpios[i]);
388c2ecf20Sopenharmony_ci	reg |= BIT(pic_raw_gpios[0]);
398c2ecf20Sopenharmony_ci	writel(reg, gpio_ctrl);
408c2ecf20Sopenharmony_ci
418c2ecf20Sopenharmony_ci	/* Prepare writing 111 to the GPIOs */
428c2ecf20Sopenharmony_ci	ackcmd = readl(gpio_ctrl);
438c2ecf20Sopenharmony_ci	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
448c2ecf20Sopenharmony_ci		ackcmd |= BIT(pic_raw_gpios[i]);
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_ci	srcmd = cpu_to_le32(srcmd);
478c2ecf20Sopenharmony_ci	ackcmd = cpu_to_le32(ackcmd);
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ci	/*
508c2ecf20Sopenharmony_ci	 * Wait a while, the PIC needs quite a bit of time between the
518c2ecf20Sopenharmony_ci	 * two GPIO commands.
528c2ecf20Sopenharmony_ci	 */
538c2ecf20Sopenharmony_ci	mdelay(3000);
548c2ecf20Sopenharmony_ci
558c2ecf20Sopenharmony_ci	asm volatile (
568c2ecf20Sopenharmony_ci		/* Align to a cache line */
578c2ecf20Sopenharmony_ci		".balign 32\n\t"
588c2ecf20Sopenharmony_ci
598c2ecf20Sopenharmony_ci		/* Enter self refresh */
608c2ecf20Sopenharmony_ci		"str %[srcmd], [%[sdram_reg]]\n\t"
618c2ecf20Sopenharmony_ci
628c2ecf20Sopenharmony_ci		/*
638c2ecf20Sopenharmony_ci		 * Wait 100 cycles for DDR to enter self refresh, by
648c2ecf20Sopenharmony_ci		 * doing 50 times two instructions.
658c2ecf20Sopenharmony_ci		 */
668c2ecf20Sopenharmony_ci		"mov r1, #50\n\t"
678c2ecf20Sopenharmony_ci		"1: subs r1, r1, #1\n\t"
688c2ecf20Sopenharmony_ci		"bne 1b\n\t"
698c2ecf20Sopenharmony_ci
708c2ecf20Sopenharmony_ci		/* Issue the command ACK */
718c2ecf20Sopenharmony_ci		"str %[ackcmd], [%[gpio_ctrl]]\n\t"
728c2ecf20Sopenharmony_ci
738c2ecf20Sopenharmony_ci		/* Trap the processor */
748c2ecf20Sopenharmony_ci		"b .\n\t"
758c2ecf20Sopenharmony_ci		: : [srcmd] "r" (srcmd), [sdram_reg] "r" (sdram_reg),
768c2ecf20Sopenharmony_ci		  [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
778c2ecf20Sopenharmony_ci}
788c2ecf20Sopenharmony_ci
798c2ecf20Sopenharmony_cistatic int __init mvebu_armada_pm_init(void)
808c2ecf20Sopenharmony_ci{
818c2ecf20Sopenharmony_ci	struct device_node *np;
828c2ecf20Sopenharmony_ci	struct device_node *gpio_ctrl_np = NULL;
838c2ecf20Sopenharmony_ci	int ret = 0, i;
848c2ecf20Sopenharmony_ci
858c2ecf20Sopenharmony_ci	if (!of_machine_is_compatible("marvell,axp-gp"))
868c2ecf20Sopenharmony_ci		return -ENODEV;
878c2ecf20Sopenharmony_ci
888c2ecf20Sopenharmony_ci	np = of_find_node_by_name(NULL, "pm_pic");
898c2ecf20Sopenharmony_ci	if (!np)
908c2ecf20Sopenharmony_ci		return -ENODEV;
918c2ecf20Sopenharmony_ci
928c2ecf20Sopenharmony_ci	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) {
938c2ecf20Sopenharmony_ci		char *name;
948c2ecf20Sopenharmony_ci		struct of_phandle_args args;
958c2ecf20Sopenharmony_ci
968c2ecf20Sopenharmony_ci		pic_gpios[i] = of_get_named_gpio(np, "ctrl-gpios", i);
978c2ecf20Sopenharmony_ci		if (pic_gpios[i] < 0) {
988c2ecf20Sopenharmony_ci			ret = -ENODEV;
998c2ecf20Sopenharmony_ci			goto out;
1008c2ecf20Sopenharmony_ci		}
1018c2ecf20Sopenharmony_ci
1028c2ecf20Sopenharmony_ci		name = kasprintf(GFP_KERNEL, "pic-pin%d", i);
1038c2ecf20Sopenharmony_ci		if (!name) {
1048c2ecf20Sopenharmony_ci			ret = -ENOMEM;
1058c2ecf20Sopenharmony_ci			goto out;
1068c2ecf20Sopenharmony_ci		}
1078c2ecf20Sopenharmony_ci
1088c2ecf20Sopenharmony_ci		ret = gpio_request(pic_gpios[i], name);
1098c2ecf20Sopenharmony_ci		if (ret < 0) {
1108c2ecf20Sopenharmony_ci			kfree(name);
1118c2ecf20Sopenharmony_ci			goto out;
1128c2ecf20Sopenharmony_ci		}
1138c2ecf20Sopenharmony_ci
1148c2ecf20Sopenharmony_ci		ret = gpio_direction_output(pic_gpios[i], 0);
1158c2ecf20Sopenharmony_ci		if (ret < 0) {
1168c2ecf20Sopenharmony_ci			gpio_free(pic_gpios[i]);
1178c2ecf20Sopenharmony_ci			kfree(name);
1188c2ecf20Sopenharmony_ci			goto out;
1198c2ecf20Sopenharmony_ci		}
1208c2ecf20Sopenharmony_ci
1218c2ecf20Sopenharmony_ci		ret = of_parse_phandle_with_fixed_args(np, "ctrl-gpios", 2,
1228c2ecf20Sopenharmony_ci						       i, &args);
1238c2ecf20Sopenharmony_ci		if (ret < 0) {
1248c2ecf20Sopenharmony_ci			gpio_free(pic_gpios[i]);
1258c2ecf20Sopenharmony_ci			kfree(name);
1268c2ecf20Sopenharmony_ci			goto out;
1278c2ecf20Sopenharmony_ci		}
1288c2ecf20Sopenharmony_ci
1298c2ecf20Sopenharmony_ci		if (gpio_ctrl_np)
1308c2ecf20Sopenharmony_ci			of_node_put(gpio_ctrl_np);
1318c2ecf20Sopenharmony_ci		gpio_ctrl_np = args.np;
1328c2ecf20Sopenharmony_ci		pic_raw_gpios[i] = args.args[0];
1338c2ecf20Sopenharmony_ci	}
1348c2ecf20Sopenharmony_ci
1358c2ecf20Sopenharmony_ci	gpio_ctrl = of_iomap(gpio_ctrl_np, 0);
1368c2ecf20Sopenharmony_ci	if (!gpio_ctrl) {
1378c2ecf20Sopenharmony_ci		ret = -ENOMEM;
1388c2ecf20Sopenharmony_ci		goto out;
1398c2ecf20Sopenharmony_ci	}
1408c2ecf20Sopenharmony_ci
1418c2ecf20Sopenharmony_ci	mvebu_pm_suspend_init(mvebu_armada_pm_enter);
1428c2ecf20Sopenharmony_ci
1438c2ecf20Sopenharmony_ciout:
1448c2ecf20Sopenharmony_ci	of_node_put(np);
1458c2ecf20Sopenharmony_ci	of_node_put(gpio_ctrl_np);
1468c2ecf20Sopenharmony_ci	return ret;
1478c2ecf20Sopenharmony_ci}
1488c2ecf20Sopenharmony_ci
1498c2ecf20Sopenharmony_ci/*
1508c2ecf20Sopenharmony_ci * Registering the mvebu_board_pm_enter callback must be done before
1518c2ecf20Sopenharmony_ci * the platform_suspend_ops will be registered. In the same time we
1528c2ecf20Sopenharmony_ci * also need to have the gpio devices registered. That's why we use a
1538c2ecf20Sopenharmony_ci * device_initcall_sync which is called after all the device_initcall
1548c2ecf20Sopenharmony_ci * (used by the gpio device) but before the late_initcall (used to
1558c2ecf20Sopenharmony_ci * register the platform_suspend_ops)
1568c2ecf20Sopenharmony_ci */
1578c2ecf20Sopenharmony_cidevice_initcall_sync(mvebu_armada_pm_init);
158