18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * arch/arm/mach-mv78xx0/db78x00-bp-setup.c 38c2ecf20Sopenharmony_ci * 48c2ecf20Sopenharmony_ci * Marvell DB-78x00-BP Development Board Setup 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * This file is licensed under the terms of the GNU General Public 78c2ecf20Sopenharmony_ci * License version 2. This program is licensed "as is" without any 88c2ecf20Sopenharmony_ci * warranty of any kind, whether express or implied. 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci#include <linux/kernel.h> 128c2ecf20Sopenharmony_ci#include <linux/init.h> 138c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 148c2ecf20Sopenharmony_ci#include <linux/ata_platform.h> 158c2ecf20Sopenharmony_ci#include <linux/mv643xx_eth.h> 168c2ecf20Sopenharmony_ci#include <linux/ethtool.h> 178c2ecf20Sopenharmony_ci#include <linux/i2c.h> 188c2ecf20Sopenharmony_ci#include <asm/mach-types.h> 198c2ecf20Sopenharmony_ci#include <asm/mach/arch.h> 208c2ecf20Sopenharmony_ci#include "mv78xx0.h" 218c2ecf20Sopenharmony_ci#include "common.h" 228c2ecf20Sopenharmony_ci 238c2ecf20Sopenharmony_cistatic struct mv643xx_eth_platform_data db78x00_ge00_data = { 248c2ecf20Sopenharmony_ci .phy_addr = MV643XX_ETH_PHY_ADDR(8), 258c2ecf20Sopenharmony_ci}; 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_cistatic struct mv643xx_eth_platform_data db78x00_ge01_data = { 288c2ecf20Sopenharmony_ci .phy_addr = MV643XX_ETH_PHY_ADDR(9), 298c2ecf20Sopenharmony_ci}; 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_cistatic struct mv643xx_eth_platform_data db78x00_ge10_data = { 328c2ecf20Sopenharmony_ci .phy_addr = MV643XX_ETH_PHY_ADDR(10), 338c2ecf20Sopenharmony_ci}; 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_cistatic struct mv643xx_eth_platform_data db78x00_ge11_data = { 368c2ecf20Sopenharmony_ci .phy_addr = MV643XX_ETH_PHY_ADDR(11), 378c2ecf20Sopenharmony_ci}; 388c2ecf20Sopenharmony_ci 398c2ecf20Sopenharmony_cistatic struct mv_sata_platform_data db78x00_sata_data = { 408c2ecf20Sopenharmony_ci .n_ports = 2, 418c2ecf20Sopenharmony_ci}; 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_cistatic struct i2c_board_info __initdata db78x00_i2c_rtc = { 448c2ecf20Sopenharmony_ci I2C_BOARD_INFO("ds1338", 0x68), 458c2ecf20Sopenharmony_ci}; 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_cistatic void __init db78x00_init(void) 498c2ecf20Sopenharmony_ci{ 508c2ecf20Sopenharmony_ci /* 518c2ecf20Sopenharmony_ci * Basic MV78xx0 setup. Needs to be called early. 528c2ecf20Sopenharmony_ci */ 538c2ecf20Sopenharmony_ci mv78xx0_init(); 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ci /* 568c2ecf20Sopenharmony_ci * Partition on-chip peripherals between the two CPU cores. 578c2ecf20Sopenharmony_ci */ 588c2ecf20Sopenharmony_ci if (mv78xx0_core_index() == 0) { 598c2ecf20Sopenharmony_ci mv78xx0_ehci0_init(); 608c2ecf20Sopenharmony_ci mv78xx0_ehci1_init(); 618c2ecf20Sopenharmony_ci mv78xx0_ehci2_init(); 628c2ecf20Sopenharmony_ci mv78xx0_ge00_init(&db78x00_ge00_data); 638c2ecf20Sopenharmony_ci mv78xx0_ge01_init(&db78x00_ge01_data); 648c2ecf20Sopenharmony_ci mv78xx0_ge10_init(&db78x00_ge10_data); 658c2ecf20Sopenharmony_ci mv78xx0_ge11_init(&db78x00_ge11_data); 668c2ecf20Sopenharmony_ci mv78xx0_sata_init(&db78x00_sata_data); 678c2ecf20Sopenharmony_ci mv78xx0_uart0_init(); 688c2ecf20Sopenharmony_ci mv78xx0_uart2_init(); 698c2ecf20Sopenharmony_ci mv78xx0_i2c_init(); 708c2ecf20Sopenharmony_ci i2c_register_board_info(0, &db78x00_i2c_rtc, 1); 718c2ecf20Sopenharmony_ci } else { 728c2ecf20Sopenharmony_ci mv78xx0_uart1_init(); 738c2ecf20Sopenharmony_ci mv78xx0_uart3_init(); 748c2ecf20Sopenharmony_ci } 758c2ecf20Sopenharmony_ci} 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_cistatic int __init db78x00_pci_init(void) 788c2ecf20Sopenharmony_ci{ 798c2ecf20Sopenharmony_ci if (machine_is_db78x00_bp()) { 808c2ecf20Sopenharmony_ci /* 818c2ecf20Sopenharmony_ci * Assign the x16 PCIe slot on the board to CPU core 828c2ecf20Sopenharmony_ci * #0, and let CPU core #1 have the four x1 slots. 838c2ecf20Sopenharmony_ci */ 848c2ecf20Sopenharmony_ci if (mv78xx0_core_index() == 0) 858c2ecf20Sopenharmony_ci mv78xx0_pcie_init(0, 1); 868c2ecf20Sopenharmony_ci else 878c2ecf20Sopenharmony_ci mv78xx0_pcie_init(1, 0); 888c2ecf20Sopenharmony_ci } 898c2ecf20Sopenharmony_ci 908c2ecf20Sopenharmony_ci return 0; 918c2ecf20Sopenharmony_ci} 928c2ecf20Sopenharmony_cisubsys_initcall(db78x00_pci_init); 938c2ecf20Sopenharmony_ci 948c2ecf20Sopenharmony_ciMACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") 958c2ecf20Sopenharmony_ci /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 968c2ecf20Sopenharmony_ci .atag_offset = 0x100, 978c2ecf20Sopenharmony_ci .nr_irqs = MV78XX0_NR_IRQS, 988c2ecf20Sopenharmony_ci .init_machine = db78x00_init, 998c2ecf20Sopenharmony_ci .map_io = mv78xx0_map_io, 1008c2ecf20Sopenharmony_ci .init_early = mv78xx0_init_early, 1018c2ecf20Sopenharmony_ci .init_irq = mv78xx0_init_irq, 1028c2ecf20Sopenharmony_ci .init_time = mv78xx0_timer_init, 1038c2ecf20Sopenharmony_ci .restart = mv78xx0_restart, 1048c2ecf20Sopenharmony_ciMACHINE_END 105