1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *   Interrupt Control Unit
4 */
5
6#ifndef __ASM_MACH_ICU_H
7#define __ASM_MACH_ICU_H
8
9#include "addr-map.h"
10
11#define ICU_VIRT_BASE	(AXI_VIRT_BASE + 0x82000)
12#define ICU_REG(x)	(ICU_VIRT_BASE + (x))
13
14#define ICU2_VIRT_BASE	(AXI_VIRT_BASE + 0x84000)
15#define ICU2_REG(x)	(ICU2_VIRT_BASE + (x))
16
17#define ICU_INT_CONF(n)		ICU_REG((n) << 2)
18#define ICU_INT_CONF_MASK	(0xf)
19
20/************ PXA168/PXA910 (MMP) *********************/
21#define ICU_INT_CONF_AP_INT	(1 << 6)
22#define ICU_INT_CONF_CP_INT	(1 << 5)
23#define ICU_INT_CONF_IRQ	(1 << 4)
24
25#define ICU_AP_FIQ_SEL_INT_NUM	ICU_REG(0x108)	/* AP FIQ Selected Interrupt */
26#define ICU_AP_IRQ_SEL_INT_NUM	ICU_REG(0x10C)	/* AP IRQ Selected Interrupt */
27#define ICU_AP_GBL_IRQ_MSK	ICU_REG(0x114)	/* AP Global Interrupt Mask */
28#define ICU_INT_STATUS_0	ICU_REG(0x128)	/* Interrupt Stuats 0 */
29#define ICU_INT_STATUS_1	ICU_REG(0x12C)	/* Interrupt Status 1 */
30
31/************************** MMP2 ***********************/
32
33/*
34 * IRQ0/FIQ0 is routed to SP IRQ/FIQ.
35 * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ.
36 */
37#define ICU_INT_ROUTE_SP_IRQ		(1 << 4)
38#define ICU_INT_ROUTE_PJ4_IRQ		(1 << 5)
39#define ICU_INT_ROUTE_PJ4_FIQ		(1 << 6)
40
41#define MMP2_ICU_PJ4_IRQ_STATUS0	ICU_REG(0x138)
42#define MMP2_ICU_PJ4_IRQ_STATUS1	ICU_REG(0x13c)
43#define MMP2_ICU_PJ4_FIQ_STATUS0	ICU_REG(0x140)
44#define MMP2_ICU_PJ4_FIQ_STATUS1	ICU_REG(0x144)
45
46#define MMP2_ICU_INT4_STATUS		ICU_REG(0x150)
47#define MMP2_ICU_INT5_STATUS		ICU_REG(0x154)
48#define MMP2_ICU_INT17_STATUS		ICU_REG(0x158)
49#define MMP2_ICU_INT35_STATUS		ICU_REG(0x15c)
50#define MMP2_ICU_INT51_STATUS		ICU_REG(0x160)
51
52#define MMP2_ICU_INT4_MASK		ICU_REG(0x168)
53#define MMP2_ICU_INT5_MASK		ICU_REG(0x16C)
54#define MMP2_ICU_INT17_MASK		ICU_REG(0x170)
55#define MMP2_ICU_INT35_MASK		ICU_REG(0x174)
56#define MMP2_ICU_INT51_MASK		ICU_REG(0x178)
57
58#define MMP2_ICU_SP_IRQ_SEL		ICU_REG(0x100)
59#define MMP2_ICU_PJ4_IRQ_SEL		ICU_REG(0x104)
60#define MMP2_ICU_PJ4_FIQ_SEL		ICU_REG(0x108)
61
62#define MMP2_ICU_INVERT			ICU_REG(0x164)
63
64#define MMP2_ICU_INV_PMIC		(1 << 0)
65#define MMP2_ICU_INV_PERF		(1 << 1)
66#define MMP2_ICU_INV_COMMTX		(1 << 2)
67#define MMP2_ICU_INV_COMMRX		(1 << 3)
68
69#endif /* __ASM_MACH_ICU_H */
70